/** @file
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GUID used for Memory Map Data entries in the HOB list.
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@copyright
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Copyright 1999 - 2021 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _MEMORY_MAP_DATA_H_
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#define _MEMORY_MAP_DATA_H_
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#include "SysHost.h"
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#include "PartialMirrorGuid.h"
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#define RESERVED_2 2
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#define RESERVED_4 4
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//
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// System Memory Map HOB information
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//
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#pragma pack(1)
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struct RankDevice {
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UINT8 enabled; // 0 = disabled, 1 = enabled
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UINT8 logicalRank; // Logical Rank number (0 - 7)
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UINT16 rankSize; // Units of 64 MB
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};
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struct PersisentDpaMap
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{
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UINT32 perRegionDPAOffset;
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UINT32 SPALimit;
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};
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typedef struct DimmDevice {
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UINT8 Present;
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BOOLEAN Enabled;
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UINT8 DcpmmPresent; // 1 - This is a DCPMM
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UINT8 X4Present;
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UINT8 NumRanks;
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UINT8 keyByte;
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UINT8 actKeyByte2; // Actual module type reported by SPD
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UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
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UINT8 dimmTs; // Thermal sensor data.
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UINT16 VolCap; // Volatile capacity (AEP DIMM only)
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UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
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UINT16 DimmSize;
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UINT32 NVmemSize;
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UINT16 SPDMMfgId; // Module Mfg Id from SPD
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UINT16 VendorID;
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UINT16 DeviceID;
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UINT16 RevisionID;
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UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
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struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
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UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
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UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
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UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
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struct firmwareRev FirmwareVersion; // Firmware revision
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struct RankDevice rankList[MAX_RANK_DIMM];
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UINT16 InterfaceFormatCode;
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UINT16 SubsystemVendorID;
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UINT16 SubsystemDeviceID;
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UINT16 SubsystemRevisionID;
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UINT16 FisVersion; // Firmware Interface Specification version
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UINT8 DimmSku; // Dimm SKU info
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UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
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UINT16 manufacturingDate; // Date the NVDIMM was manufactured
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INT32 commonTck;
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UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
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BOOLEAN NvDimmNPresent; ///< JEDEC NVDIMM-N Type Memory Present
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UINT16 SPDRegVen; ///< Register Vendor ID in SPD
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UINT8 CidBitMap; // SubRankPer CS for DIMM device
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} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
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struct ChannelDevice {
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UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
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UINT8 Features; // Bit mask of features to enable or disable
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UINT8 MaxDimm; // Number of DIMM
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UINT8 NumRanks; // Number of ranks on this channel
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UINT8 chFailed;
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UINT8 ngnChFailed;
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UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
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UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
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UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
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UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
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MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
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};
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struct memcontroller {
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UINT32 MemSize;
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};
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typedef struct socket {
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UINT8 SocketEnabled;
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UINT16 IioStackBitmap;
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BOOLEAN Reserved[RESERVED_4];
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UINT8 imcEnabled[MAX_IMC];
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UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][MC_MAX_NODE]; // SAD interleave list
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UINT8 SktSkuValid; // Whether Socket SKU value is valid from PCU
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UINT32 SktSkuLimit; // SKU limit value from PCU
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UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
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UINT32 SktPmemMapSpa; // Total persistent memory mapped to SPA
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UINT32 SktMemSize2LM; // Total memory excluded from Limit
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SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
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struct memcontroller imc[MAX_IMC];
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struct ChannelDevice ChannelInfo[MAX_CH];
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} MEMMAP_SOCKET;
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typedef struct SystemMemoryMapElement {
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UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
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UINT8 NodeId; // Node ID of the HA Owning the memory
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UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
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UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
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UINT8 ImcInterBitmap; // IMC interleave bitmap for this memory
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UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
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UINT32 BaseAddress; // Base Address of the element in 64MB chunks
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UINT32 ElementSize; // Size of this memory element in 64MB chunks
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} SYSTEM_MEMORY_MAP_ELEMENT;
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typedef struct SystemMemoryMapHob {
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//
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// Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters.
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// All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
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//
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UINT8 TotalClusters;
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MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure
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UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
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UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
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UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
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UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem.
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UINT32 memSize; // Total physical memory size
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UINT16 memFreq; // Mem Frequency
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UINT8 memMode; // 0 - Independent, 1 - Lockstep
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UINT8 volMemMode; // 0 - 1LM, 1 - 2LM
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UINT8 CacheMemType; // 0 - DDR$DDRT
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UINT8 DdrtIntlvGranularity; // 1 - 256B, 2 - 4KB
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UINT16 DramType;
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UINT8 SmbMode[MAX_SOCKET][MAX_SMB_INSTANCE]; // Stores type of smbus mode: 0 - I2C mode, 1 - I3C mode
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UINT8 DdrVoltage;
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UINT8 DcpmmPresent; // If at least one DCPMM Present (used by Nfit), then this should get set
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BOOLEAN EkvPresent; // Set if EKV controller on system
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BOOLEAN BwvPresent; // Set if BWV controller on system
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UINT8 XMPProfilesSup;
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UINT16 Reserved1[MAX_SOCKET];
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UINT32 Reserved2;
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UINT32 Reserved3;
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UINT16 Reserved4;
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UINT16 Reserved5;
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UINT8 SystemRasType;
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UINT8 RasModesEnabled; // RAS modes that are enabled
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UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
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UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
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UINT8 NumOfCluster;
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UINT8 NumChPerMC;
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UINT8 numberEntries; // Number of Memory Map Elements
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SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
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struct memSetup MemSetup;
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MEM_RESERVED_1 Reserved142;
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MEMMAP_SOCKET Socket[MAX_SOCKET];
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struct memTiming profileMemTime[2];
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UINT32 Reserved6;
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UINT8 Reserved7[RESERVED_2];
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EFI_GUID Reserved8[RESERVED_2];
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UINT8 Reserved9;
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RASMEMORYINFO RasMeminfo;
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UINT8 LatchSystemShutdownState;
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BOOLEAN IsWpqFlushSupported;
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UINT8 EadrSupport;
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UINT8 EadrCacheFlushMode;
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UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH
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HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH];
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UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
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BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules
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UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
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UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW)
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UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW)
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UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power
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UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW).
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UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW).
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UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power
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UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant
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UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant
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UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant
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UINT32 MmiohBase; // MMIOH base in 64MB granularity
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UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon)
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UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
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UINT8 VirtualNumaEnable; // Enable or Disable Virtual NUMA
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UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster)
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BOOLEAN NumaEnable; // Information if NUMA is enabled or not
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} SYSTEM_MEMORY_MAP_HOB;
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#pragma pack()
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#endif // _MEMORY_MAP_DATA_H_
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