/** @file
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This SMM driver will handle SA relevant late initialization
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/BaseLib.h>
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#include <Base.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/DxeServicesTableLib.h>
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#include <Library/SmmServicesTableLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/HobLib.h>
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#include <Library/SaPlatformLib.h>
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#include <Protocol/SmmIoTrapDispatch2.h>
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#include "SaLateInitSmm.h"
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#include <Library/PciSegmentLib.h>
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#include <CpuDataStruct.h>
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#include <CpuPcieHob.h>
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#include <Protocol/SaIotrapSmi.h>
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#include <PchPcieRpConfig.h>
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#include <SaConfigHob.h>
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#include "CpuPcieInfo.h"
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#include <Register/CpuPcieRegs.h>
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#include <IndustryStandard/Pci30.h>
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#include <Register/IgdRegs.h>
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#include <Register/CommonMsr.h>
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typedef enum {
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EnumSaSmiCallbackForMaxPayLoad,
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EnumSaSmiCallbackForSaSaveRestore,
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EnumSaSmiCallbackForLateInit,
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EnumSaSmiCallbackForS3resume,
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EnumSaSmiCallbackMax
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} SMI_OPERATION;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSaSmiCallbackPhase = EnumSaSmiCallbackForMaxPayLoad;
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mPchIoTrap;
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SX_DISPATCH2_PROTOCOL *mSxDispatch;
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typedef struct {
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UINT64 BaseAddr;
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UINT32 Offset;
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UINT32 AndMask;
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UINT32 OrMask;
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} BOOT_SCRIPT_REGISTER_SETTING;
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/**
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Initializes the SA SMM handler
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@param[in] ImageHandle - The image handle of Wake On Lan driver
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@param[in] SystemTable - The standard EFI system table
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@retval EFI_SUCCESS - SA SMM handler was installed or not necessary
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@retval EFI_NOT_FOUND - Fail to register SMI callback or required protocol/hob missing.
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**/
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EFI_STATUS
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EFIAPI
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SaLateInitSmmEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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#if FixedPcdGetBool(PcdCpuPcieEnable) == 1
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CPU_PCIE_HOB *CpuPcieHob = NULL;
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EFI_STATUS Status;
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#endif
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DEBUG ((DEBUG_INFO, "SaLateInitSmmEntryPoint()\n"));
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#if FixedPcdGetBool(PcdCpuPcieEnable) == 1
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CpuPcieHob = (CPU_PCIE_HOB *) GetFirstGuidHob (&gCpuPcieHobGuid);
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Status = EFI_NOT_FOUND;
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if (CpuPcieHob == NULL) {
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DEBUG ((DEBUG_INFO, "CPU PCIE HOB Not found\n"));
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ASSERT (CpuPcieHob != NULL);
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return Status;
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}
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///
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/// Locate the PCH Trap dispatch protocol
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///
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Status = gSmst->SmmLocateProtocol (&gEfiSmmIoTrapDispatch2ProtocolGuid, NULL, (VOID **) &mPchIoTrap);
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ASSERT_EFI_ERROR (Status);
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Status = gSmst->SmmLocateProtocol (&gEfiSmmSxDispatch2ProtocolGuid, NULL, (VOID**) &mSxDispatch);
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ASSERT_EFI_ERROR (Status);
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if (Status == EFI_SUCCESS) {
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///
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/// If ASPM policy is set to "Before OPROM", this SMI callback is not necessary
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/// Ensure the SMI callback handler will directly return and continue the POST.
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///
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mSaSmiCallbackPhase = EnumSaSmiCallbackMax;
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Status = EFI_SUCCESS;
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}
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Status = InitializeCpuPcieSmm (ImageHandle, SystemTable);
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ASSERT_EFI_ERROR (Status);
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if (Status != EFI_SUCCESS) {
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DEBUG ((DEBUG_ERROR, "Failed to register SaIotrapSmiCallback!\n"));
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///
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/// System will halt when failing to register required SMI handler
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///
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CpuDeadLoop ();
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}
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#endif
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return EFI_SUCCESS;
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}
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