/** @file
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PCH Init Smm module for PCH specific SMI handlers.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PchInitSmm.h"
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#include <Register/PchRegs.h>
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#include <Register/UsbRegs.h>
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#include <Register/SmbusRegs.h>
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#include <Library/PchPciBdfLib.h>
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mPchIoTrap;
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SX_DISPATCH2_PROTOCOL *mSxDispatch;
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_NVS_AREA *mPchNvsArea;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
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GLOBAL_REMOVE_IF_UNREFERENCED FIVR_EXT_RAIL_CONFIG mFivrExtVnnRailSxConfig;
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//
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// NOTE: The module variables of policy here are only valid in post time, but not runtime time.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *mPchConfigHob;
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//
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// The reserved MMIO range to be used in Sx handler
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//
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mResvMmioBaseAddr;
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GLOBAL_REMOVE_IF_UNREFERENCED UINTN mResvMmioSize;
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/**
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SMBUS Sx entry SMI handler.
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**/
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VOID
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SmbusSxCallback (
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VOID
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)
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{
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UINT64 SmbusRegBase;
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UINT16 SmbusIoBase;
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SmbusRegBase = SmbusPciCfgBase ();
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if (PciSegmentRead32 (SmbusRegBase) == 0xFFFFFFFF) {
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return;
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}
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SmbusIoBase = PciSegmentRead16 (SmbusRegBase + R_SMBUS_CFG_BASE) & B_SMBUS_CFG_BASE_BAR;
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if (SmbusIoBase == 0) {
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return;
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}
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PciSegmentOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE);
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//
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// Clear SMBUS status and SMB_WAK_STS of GPE0
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//
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IoWrite8 (SmbusIoBase + R_SMBUS_IO_HSTS, B_SMBUS_IO_SMBALERT_STS);
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IoWrite32 (mAcpiBaseAddr + R_ACPI_IO_GPE0_STS_127_96, B_ACPI_IO_GPE0_STS_127_96_SMB_WAK);
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}
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/*
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PCH xHCI Sx entry SMI handler
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*/
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VOID
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PchXhciSxCallback (
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VOID
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)
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{
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UINTN XhciPciBase;
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XhciPciBase = PchXhciPciCfgBase ();
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//
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// Safety check for xHCI existense
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//
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if (PciSegmentRead32 (XhciPciBase) == 0xFFFFFFFF) {
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return;
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}
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//
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// If xHCI is in D0 that means OS didn't put it to D3 during Sx entry i.e. USB kernel debug is enabled.
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// Unless it is put manually to D3, USB wake functionality will not work.
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//
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if ((PciSegmentRead8 (XhciPciBase + R_XHCI_CFG_PWR_CNTL_STS) & V_XHCI_CFG_PWR_CNTL_STS_PWR_STS_D3) == 0) {
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//
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// Put device to D3 to enable wake functionality for USB devices
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//
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PciSegmentOr8 (XhciPciBase + R_XHCI_CFG_PWR_CNTL_STS, (UINT8)(B_XHCI_CFG_PWR_CNTL_STS_PWR_STS));
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}
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}
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/**
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Cache PCH FIVR policy.
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**/
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VOID
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UpdatePchFivrSettings (
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VOID
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)
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{
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CopyMem (
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&mFivrExtVnnRailSxConfig,
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&mPchConfigHob->Fivr.ExtVnnRailSx,
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sizeof (mFivrExtVnnRailSxConfig)
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);
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}
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/**
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PCH Sx entry SMI handler.
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@param[in] Handle Handle of the callback
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@param[in] Context The dispatch context
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@param[in,out] CommBuffer A pointer to a collection of data in memory that will
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be conveyed from a non-SMM environment into an SMM environment.
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@param[in,out] CommBufferSize The size of the CommBuffer.
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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EFIAPI
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PchSxHandler (
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IN EFI_HANDLE Handle,
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IN CONST VOID *Context OPTIONAL,
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IN OUT VOID *CommBuffer OPTIONAL,
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IN OUT UINTN *CommBufferSize OPTIONAL
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)
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{
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PchLanSxCallback ();
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PchXhciSxCallback ();
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SmbusSxCallback ();
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return EFI_SUCCESS;
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}
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/**
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Initialize PCH Sx entry SMI handler.
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@param[in] ImageHandle - Handle for the image of this driver
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**/
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VOID
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InitializeSxHandler (
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IN EFI_HANDLE ImageHandle
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)
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{
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EFI_SMM_SX_REGISTER_CONTEXT SxDispatchContext;
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EFI_HANDLE SxDispatchHandle;
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EFI_SLEEP_TYPE SxType;
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "InitializeSxHandler() Start\n"));
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//
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// Register the callback for S3/S4/S5 entry
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//
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SxDispatchContext.Phase = SxEntry;
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for (SxType = SxS3; SxType <= SxS5; SxType++) {
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SxDispatchContext.Type = SxType;
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Status = mSxDispatch->Register (
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mSxDispatch,
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PchSxHandler,
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&SxDispatchContext,
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&SxDispatchHandle
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);
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ASSERT_EFI_ERROR (Status);
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}
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DEBUG ((DEBUG_INFO, "InitializeSxHandler() End\n"));
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}
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/**
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Allocates reserved MMIO for Sx SMI handler use.
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**/
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VOID
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AllocateReservedMmio (
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VOID
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)
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{
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mResvMmioBaseAddr = PcdGet32 (PcdSiliconInitTempMemBaseAddr);
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mResvMmioSize = PcdGet32 (PcdSiliconInitTempMemSize);
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DEBUG ((DEBUG_INFO, "mResvMmioBaseAddr %x, mResvMmioSize %x\n", mResvMmioBaseAddr, mResvMmioSize));
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}
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/**
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Initializes the PCH SMM handler for for PCIE hot plug support
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<b>PchInit SMM Module Entry Point</b>\n
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- <b>Introduction</b>\n
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The PchInitSmm module is a SMM driver that initializes the Intel Platform Controller Hub
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SMM requirements and services. It consumes the PCH_POLICY_HOB and SI_POLICY_HOB for expected
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configurations per policy.
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- <b>Details</b>\n
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This module provides SMI handlers to services PCIE HotPlug SMI, LinkActive SMI, and LinkEq SMI.
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And also provides port 0x61 emulation support, registers BIOS WP handler to process BIOSWP status,
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and registers SPI Async SMI handler to handler SPI Async SMI.
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This module also registers Sx SMI callback function to detail with GPIO Sx Isolation and LAN requirement.
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- @pre
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- PCH PCR base address configured
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- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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- This is to ensure that PCI MMIO and IO resource has been prepared and available for this driver to allocate.
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- EFI_SMM_BASE2_PROTOCOL
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- EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL
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- EFI_SMM_SX_DISPATCH2_PROTOCOL
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- EFI_SMM_CPU_PROTOCOL
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- @link _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROTOCOL @endlink
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- @link _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL @endlink
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- @link _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL @endlink
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- @link _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL @endlink
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- @link _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTOCOL @endlink
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- <b>References</b>\n
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- @link _PCH_POLICY PCH_POLICY_HOB @endlink.
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- @link _SI_POLICY_STRUCT SI_POLICY_HOB @endlink.
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- <b>Integration Checklists</b>\n
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- Verify prerequisites are met. Porting Recommendations.
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- No modification of this module should be necessary
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- Any modification of this module should follow the PCH BIOS Specification and EDS
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@param[in] ImageHandle - Handle for the image of this driver
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@param[in] SystemTable - Pointer to the EFI System Table
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@retval EFI_SUCCESS - PCH SMM handler was installed
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**/
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EFI_STATUS
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EFIAPI
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PchInitSmmEntryPoint (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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PCH_NVS_AREA_PROTOCOL *PchNvsAreaProtocol;
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EFI_PEI_HOB_POINTERS HobPtr;
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DEBUG ((DEBUG_INFO, "PchInitSmmEntryPoint()\n"));
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Status = gSmst->SmmLocateProtocol (
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&gEfiSmmIoTrapDispatch2ProtocolGuid,
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NULL,
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(VOID **) &mPchIoTrap
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);
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ASSERT_EFI_ERROR (Status);
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Status = gSmst->SmmLocateProtocol (
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&gEfiSmmSxDispatch2ProtocolGuid,
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NULL,
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(VOID**) &mSxDispatch
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);
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ASSERT_EFI_ERROR (Status);
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Status = gBS->LocateProtocol (&gPchNvsAreaProtocolGuid, NULL, (VOID **) &PchNvsAreaProtocol);
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ASSERT_EFI_ERROR (Status);
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mPchNvsArea = PchNvsAreaProtocol->Area;
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//
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// Get PCH Data HOB.
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//
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HobPtr.Guid = GetFirstGuidHob (&gPchConfigHobGuid);
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ASSERT (HobPtr.Guid != NULL);
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mPchConfigHob = (PCH_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid);
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mAcpiBaseAddr = PmcGetAcpiBase ();
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AllocateReservedMmio ();
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InitializeSxHandler (ImageHandle);
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Status = InitializePchPcieSmm (ImageHandle, SystemTable);
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ASSERT_EFI_ERROR (Status);
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Status = InstallPchBiosWriteProtect (ImageHandle, SystemTable);
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ASSERT_EFI_ERROR (Status);
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Status = InstallPchSpiAsyncSmiHandler ();
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ASSERT_EFI_ERROR (Status);
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UpdateHdaCodecSxWakeCapabilitySetting ();
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UpdatePchFivrSettings ();
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return EFI_SUCCESS;
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}
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