/** @file
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This is the Uefi driver that initializes the Intel PCH.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/UefiLib.h>
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#include "PchInit.h"
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#include <PchPolicyCommon.h>
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#include <Protocol/PcieIoTrap.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PmcLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/PmcPrivateLib.h>
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#include <Library/PciExpressHelpersLib.h>
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#include <PcieRegs.h>
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#include <Register/PchPcieRpRegs.h>
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#include <Register/PmcRegs.h>
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_HANDLE mImageHandle;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPcieIoTrapAddress;
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VOID
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EFIAPI
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PchOnBootToOs (
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IN EFI_EVENT Event,
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IN VOID *Context
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);
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VOID
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EFIAPI
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PchOnExitBootServices (
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IN EFI_EVENT Event,
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IN VOID *Context
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);
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VOID
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EFIAPI
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PchOnReadyToBoot (
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IN EFI_EVENT Event,
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IN VOID *Context
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);
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/**
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Process all the lock downs
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**/
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VOID
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ProcessSmiLocks (
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VOID
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)
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{
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UINT32 Data32And;
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UINT32 Data32Or;
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UINT16 ABase;
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// BIOS needs to enables SMI_LOCK (PMC PCI offset A0h[4] = 1b) which prevent writes
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/// to the Global SMI Enable bit (GLB_SMI_EN ABASE + 30h[0]). Enabling this bit will
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/// mitigate malicious software attempts to gain system management mode privileges.
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///
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if (mPchConfigHob->LockDown.GlobalSmi == TRUE) {
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///
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/// Save Global SMI Enable bit setting before BIOS enables SMI_LOCK during S3 resume
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///
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ABase = PmcGetAcpiBase ();
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Data32Or = IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN));
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if ((Data32Or & B_ACPI_IO_SMI_EN_GBL_SMI) != 0) {
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Data32And = 0xFFFFFFFF;
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Data32Or |= B_ACPI_IO_SMI_EN_GBL_SMI;
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S3BootScriptSaveIoReadWrite (
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S3BootScriptWidthUint32,
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(UINTN) (ABase + R_ACPI_IO_SMI_EN),
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&Data32Or, // Data to be ORed
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&Data32And // Data to be ANDed
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);
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}
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PmcLockSmiWithS3BootScript ();
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}
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}
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/**
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Do PCIE power management while resume from S3
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**/
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VOID
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ReconfigurePciePowerManagementForS3 (
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VOID
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)
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{
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EFI_STATUS Status;
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UINT32 Data32;
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PCH_PCIE_IOTRAP_PROTOCOL *PchPcieIoTrapProtocol;
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Status = gBS->LocateProtocol (&gPchPcieIoTrapProtocolGuid, NULL, (VOID **) &PchPcieIoTrapProtocol);
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if (EFI_ERROR (Status)) {
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return;
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}
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mPcieIoTrapAddress = PchPcieIoTrapProtocol->PcieTrapAddress;
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DEBUG ((DEBUG_INFO, "PcieIoTrapAddress: %0x\n", mPcieIoTrapAddress));
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if (mPcieIoTrapAddress != 0) {
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//
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// Save PCH PCIE IoTrap address to re-config PCIE power management setting after resume from S3
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//
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Data32 = PchPciePmTrap;
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S3BootScriptSaveIoWrite (
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S3BootScriptWidthUint32,
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(UINTN) (mPcieIoTrapAddress),
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1,
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&Data32
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);
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} else {
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ASSERT (FALSE);
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}
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}
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/**
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This is the callback function for PCI ENUMERATION COMPLETE.
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**/
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VOID
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EFIAPI
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PchOnPciEnumComplete (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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EFI_STATUS Status;
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VOID *ProtocolPointer;
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///
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/// Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
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/// if it is, we will skip it until real event is triggered
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///
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Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **) &ProtocolPointer);
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if (EFI_SUCCESS != Status) {
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return;
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}
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gBS->CloseEvent (Event);
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ReconfigurePciePowerManagementForS3 ();
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ProcessSmiLocks ();
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ConfigureSerialIoAtS3Resume ();
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}
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/**
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Register callback functions for PCH DXE.
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**/
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VOID
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PchRegisterNotifications (
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VOID
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)
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{
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EFI_STATUS Status;
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EFI_EVENT ReadyToBoot;
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EFI_EVENT LegacyBootEvent;
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EFI_EVENT ExitBootServicesEvent;
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VOID *Registration;
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///
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/// Create PCI Enumeration Completed callback for PCH
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///
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EfiCreateProtocolNotifyEvent (
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&gEfiPciEnumerationCompleteProtocolGuid,
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TPL_CALLBACK,
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PchOnPciEnumComplete,
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NULL,
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&Registration
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);
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//
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// Register a Ready to boot event to config PCIE power management setting after OPROM executed
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//
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Status = EfiCreateEventReadyToBootEx (
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TPL_CALLBACK,
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PchOnReadyToBoot,
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NULL,
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&ReadyToBoot
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Create events for PCH to do the task before ExitBootServices/LegacyBoot.
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// It is guaranteed that only one of two events below will be signalled
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//
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Status = gBS->CreateEvent (
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EVT_SIGNAL_EXIT_BOOT_SERVICES,
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TPL_CALLBACK,
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PchOnExitBootServices,
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NULL,
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&ExitBootServicesEvent
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);
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ASSERT_EFI_ERROR (Status);
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Status = EfiCreateEventLegacyBootEx (
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TPL_CALLBACK,
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PchOnBootToOs,
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NULL,
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&LegacyBootEvent
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);
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ASSERT_EFI_ERROR (Status);
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}
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/**
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<b>PchInit DXE Module Entry Point</b>\n
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- <b>Introduction</b>\n
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The PchInit module is a DXE driver that initializes the Intel Platform Controller Hub
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following the PCH BIOS specification and EDS requirements and recommendations. It consumes
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the PCH_POLICY_HOB SI_POLICY_HOB for expected configurations per policy.
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This is the standard EFI driver point that detects whether there is an supported PCH in
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the system and if so, initializes the chipset.
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- <b>Details</b>\n
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This module is required for initializing the Intel Platform Controller Hub to
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follow the PCH BIOS specification and EDS.
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This includes some initialization sequences, enabling and disabling PCH devices,
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configuring clock gating, RST PCIe Storage Remapping, SATA controller, ASPM of PCIE devices. Right before end of DXE,
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it's responsible to lock down registers for security requirement.
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- @pre
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- PCH PCR base address configured
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- EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
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- This is to ensure that PCI MMIO and IO resource has been prepared and available for this driver to allocate.
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- @result
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- Publishes the @link _PCH_INFO_PROTOCOL PCH_INFO_PROTOCOL @endlink
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- Publishes the @link _PCH_EMMC_TUNING_PROTOCOL PCH_EMMC_TUNING_PROTOCOL @endlink
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- <b>References</b>\n
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- @link _PCH_POLICY PCH_POLICY_HOB @endlink.
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- @link _SI_POLICY_STRUCT SI_POLICY_HOB @endlink.
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- <b>Integration Checklists</b>\n
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- Verify prerequisites are met. Porting Recommendations.
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- No modification of this module should be necessary
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- Any modification of this module should follow the PCH BIOS Specification and EDS
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@param[in] ImageHandle Handle for the image of this driver
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@param[in] SystemTable Pointer to the EFI System Table
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
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**/
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EFI_STATUS
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EFIAPI
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PchInitEntryPointDxe (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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DEBUG ((DEBUG_INFO, "PchInitEntryPointDxe() Start\n"));
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mImageHandle = ImageHandle;
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PchInitEntryPointCommon ();
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Status = PchAcpiInit (ImageHandle);
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PchRegisterNotifications ();
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CreateSerialIoUartHiddenHandle ();
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DEBUG ((DEBUG_INFO, "PchInitEntryPointDxe() End\n"));
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return Status;
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}
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/**
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PCH initialization before ExitBootServices / LegacyBoot events
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Useful for operations which must happen later than at EndOfPost event
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@param[in] Event A pointer to the Event that triggered the callback.
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@param[in] Context A pointer to private data registered with the callback function.
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**/
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VOID
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EFIAPI
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PchOnBootToOs (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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///
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/// Closed the event to avoid call twice
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///
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if (Event != NULL) {
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gBS->CloseEvent (Event);
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}
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ConfigureSerialIoAtBoot ();
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return;
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}
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/**
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PCH initialization on ExitBootService. This event is used if only ExitBootService is used
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and not in legacy boot
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@param[in] Event A pointer to the Event that triggered the callback.
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@param[in] Context A pointer to private data registered with the callback function.
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@retval None
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**/
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VOID
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EFIAPI
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PchOnExitBootServices (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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PchOnBootToOs (NULL, NULL);
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return;
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}
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/**
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PCH initialization before boot to OS
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@param[in] Event A pointer to the Event that triggered the callback.
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@param[in] Context A pointer to private data registered with the callback function.
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**/
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VOID
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EFIAPI
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PchOnReadyToBoot (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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DEBUG ((DEBUG_INFO, "Uefi PchOnReadyToBoot() Start\n"));
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if (Event != NULL) {
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gBS->CloseEvent (Event);
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}
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//
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// Trigger an Iotrap SMI to config PCIE power management setting after PCI enumrate is done
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//
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if (mPcieIoTrapAddress != 0) {
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IoWrite32 ((UINTN) mPcieIoTrapAddress, PchPciePmTrap);
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} else {
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ASSERT (FALSE);
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}
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DEBUG ((DEBUG_INFO, "Uefi PchOnReadyToBoot() End\n"));
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}
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