/** @file
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This file contains definitions of PCH Info HOB.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_INFO_HOB_H_
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#define _PCH_INFO_HOB_H_
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extern EFI_GUID gPchInfoHobGuid;
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#define PCH_INFO_HOB_REVISION 4
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#pragma pack (push,1)
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/**
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This structure is used to provide the information of PCH controller.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Add CridSupport, CridOrgRid, and CridNewRid.
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<b>Revision 3</b>:
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- Add Thc0Strap.
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<b>Revision 4</b>
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- Removed GbePciePortNumber
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**/
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typedef struct {
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/**
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This member specifies the revision of the PCH Info HOB. This field is used
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to indicate backwards compatible changes to the protocol. Platform code that
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consumes this protocol must read the correct revision value to correctly interpret
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the content of the protocol fields.
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**/
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UINT8 Revision;
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UINT8 PcieControllerCfg[6];
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/**
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THC strap disable/enable status
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**/
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UINT8 Thc0Strap;
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UINT32 PciePortFuses;
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/**
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Bit map for PCIe Root Port Lane setting. If bit is set it means that
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corresponding Root Port has its lane enabled.
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BIT0 - RP0, BIT1 - RP1, ...
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This information needs to be passed through HOB as FIA registers
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are not accessible with POSTBOOT_SAI
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**/
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UINT32 PciePortLaneEnabled;
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/**
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Publish Hpet BDF and IoApic BDF information for VTD.
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**/
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UINT32 HpetBusNum : 8;
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UINT32 HpetDevNum : 5;
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UINT32 HpetFuncNum : 3;
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UINT32 IoApicBusNum : 8;
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UINT32 IoApicDevNum : 5;
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UINT32 IoApicFuncNum : 3;
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/**
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Publish the CRID information.
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**/
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UINT32 CridOrgRid : 8;
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UINT32 CridNewRid : 8;
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UINT32 CridSupport : 1;
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UINT32 Rsvdbits : 15;
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} PCH_INFO_HOB;
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#pragma pack (pop)
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#endif // _PCH_INFO_HOB_H_
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