/** @file
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PCH private PMC Library for all PCH generations.
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All function in this library is available for PEI, DXE, and SMM,
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But do not support UEFI RUNTIME environment call.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PmcLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PmcPrivateLib.h>
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/**
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This function checks if GbE device is supported (not disabled by fuse)
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@retval GbE support state
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**/
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BOOLEAN
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PmcIsGbeSupported (
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VOID
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)
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{
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//
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// Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS) == 0);
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}
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/**
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This function checks if LAN wake from DeepSx is enabled
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@retval Lan Wake state
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**/
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BOOLEAN
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PmcIsLanDeepSxWakeEnabled (
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VOID
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)
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{
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//
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// Get wake info from PWRMBASE + DSX_CFG
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//
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return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_DSX_CFG) & (UINT32) B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN) != 0);
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}
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/**
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This function checks if eSPI SMI Lock is set
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@retval eSPI SMI Lock state
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**/
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BOOLEAN
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PmcIsEspiSmiLockSet (
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VOID
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)
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{
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return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A)) & B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK) != 0);
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}
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/**
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This function sets SW SMI Rate.
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@param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
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**/
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VOID
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PmcSetSwSmiRate (
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IN PMC_SWSMI_RATE SwSmiRate
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)
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{
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UINT32 PchPwrmBase;
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STATIC UINT8 SwSmiRateRegVal[4] = {
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V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS,
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V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS,
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V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS,
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V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS
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};
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ASSERT (SwSmiRate <= PmcSwSmiRate64ms);
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PchPwrmBase = PmcGetPwrmBase ();
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//
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// SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well
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//
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MmioAndThenOr8 (
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PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
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(UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL,
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SwSmiRateRegVal[SwSmiRate]
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);
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}
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/**
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This function sets Periodic SMI Rate.
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@param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
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**/
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VOID
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PmcSetPeriodicSmiRate (
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IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
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)
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{
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UINT32 PchPwrmBase;
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STATIC UINT8 PeriodicSmiRateRegVal[4] = {
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V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S,
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V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S,
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V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S,
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V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S
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};
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ASSERT (PeriodicSmiRate <= PmcPeriodicSmiRate64s);
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PchPwrmBase = PmcGetPwrmBase ();
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MmioAndThenOr8 (
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PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
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(UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL,
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PeriodicSmiRateRegVal[PeriodicSmiRate]
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);
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}
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/**
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This function reads Power Button Level
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@retval State of PWRBTN# signal (0: Low, 1: High)
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**/
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UINT8
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PmcGetPwrBtnLevel (
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VOID
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)
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{
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if (MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL) {
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return 1;
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} else {
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return 0;
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}
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}
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/**
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This function gets Group to GPE0 configuration
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@param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment
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@param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment
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@param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment
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**/
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VOID
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PmcGetGpioGpe (
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OUT UINT32 *GpeDw0Value,
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OUT UINT32 *GpeDw1Value,
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OUT UINT32 *GpeDw2Value
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)
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{
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UINT32 Data32;
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Data32 = MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GPIO_CFG));
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*GpeDw0Value = ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW0) >> N_PMC_PWRM_GPIO_CFG_GPE0_DW0);
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*GpeDw1Value = ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW1) >> N_PMC_PWRM_GPIO_CFG_GPE0_DW1);
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*GpeDw2Value = ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW2) >> N_PMC_PWRM_GPIO_CFG_GPE0_DW2);
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}
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