/** @file
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This file contains routines that support PCI Express initialization
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/PcieHelperLib.h>
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#include <Library/PchSbiAccessLib.h>
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#include <Library/PchPciBdfLib.h>
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#include <Library/PcieRpLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/PsfLib.h>
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#include <Library/HobLib.h>
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#include <Register/PchPcieRpRegs.h>
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#include <Register/PcieSipRegs.h>
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#include <PcieRegs.h>
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#include <PchPcieRpInfo.h>
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#include <CpuPcieInfo.h>
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#include <CpuPcieHob.h>
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/**
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Get PCIe port number for enabled port.
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@param[in] RpBase Root Port pci segment base address
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@retval Root Port number (1 based)
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**/
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UINT32
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PciePortNum (
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IN UINT64 RpBase
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)
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{
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return PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LCAP) >> N_PCH_PCIE_CFG_LCAP_PN;
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}
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/**
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Get PCIe root port index
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@param[in] RpBase Root Port pci segment base address
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@retval Root Port index (0 based)
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**/
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UINT32
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PciePortIndex (
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IN UINT64 RpBase
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)
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{
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return PciePortNum (RpBase) - 1;
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}
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/**
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This function checks whether PHY lane power gating is enabled on the port.
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@param[in] RpBase Root Port base address
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@retval TRUE PHY power gating is enabled
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@retval FALSE PHY power gating disabled
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**/
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BOOLEAN
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PcieIsPhyLanePgEnabled (
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IN UINT64 RpBase
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)
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{
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UINT32 Data32;
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Data32 = PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL);
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return (Data32 & B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE) != 0;
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}
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/**
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Configures Root Port packet split.
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@param[in] Segment,Bus,Device,Function address of currently visited PCIe device
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@param[in] Mps maximum packet size
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**/
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VOID
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ConfigureRpPacketSplit (
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UINT64 RpBase,
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UINT8 Mps
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)
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{
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PciSegmentAndThenOr32 (RpBase + R_PCIE_CFG_CCFG, (UINT32) ~(B_PCIE_CFG_CCFG_UNRS), Mps << N_PCIE_CFG_CCFG_UNRS);
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}
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/**
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Configures LTR override in Root Port's proprietary registers.
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@param[in] Segment,Bus,Device,Function address of currently visited PCIe device
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@param[in] DevNum currently visited device number
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@param[in] RpConfig Root Port LTR configuration
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@param[in] AspmOverride combination of LTR override values from all devices under this Root Port
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**/
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VOID
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ConfigureRpLtrOverride (
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UINT64 RpBase,
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UINT32 DevNum,
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LTR_OVERRIDE *TreeLtr,
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PCIE_LTR_CONFIG *LtrConfig
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)
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{
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UINT32 OvrEn;
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UINT32 OvrVal;
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BOOLEAN IsCpuPcie;
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IsCpuPcie = FALSE;
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OvrEn = 0;
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OvrVal = 0;
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if (DevNum == SA_PEG0_DEV_NUM || DevNum == SA_PEG3_DEV_NUM) {
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IsCpuPcie = TRUE;
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}
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//
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// LTR settings from LTROVR register only get acknowledged on rising edge of LTROVR2[1:0]
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// If those bits were already set (that can happen on a plug-hotUnplug-hotPlug scenario),
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// they need to be toggled
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//
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if (PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LTROVR2) != 0) {
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PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_LTROVR2, 0);
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}
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//
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// (*)LatencyOverrideMode = 0 -> no override
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// 1 -> override with RP policy values
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// 2 -> override with endpoint's override values
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//
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if (LtrConfig->ForceLtrOverride || TreeLtr->ForceOverride) {
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OvrEn |= B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE;
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}
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if (LtrConfig->LtrConfigLock == TRUE) {
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OvrEn |= B_PCH_PCIE_CFG_LTROVR2_LOCK;
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}
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if (LtrConfig->SnoopLatencyOverrideMode == 1) {
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OvrEn |= B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN;
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OvrVal |= LtrConfig->SnoopLatencyOverrideValue;
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OvrVal |= LtrConfig->SnoopLatencyOverrideMultiplier << 10;
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OvrVal |= B_PCH_PCIE_CFG_LTROVR_LTRSROVR;
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} else if (LtrConfig->SnoopLatencyOverrideMode == 2) {
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if (TreeLtr->MaxSnoopLatencyRequirement) {
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OvrEn |= B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN;
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OvrVal |= TreeLtr->MaxSnoopLatencyValue;
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OvrVal |= TreeLtr->MaxSnoopLatencyScale << 10;
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OvrVal |= B_PCH_PCIE_CFG_LTROVR_LTRSROVR;
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}
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}
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if (LtrConfig->NonSnoopLatencyOverrideMode == 1) {
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OvrEn |= B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN;
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OvrVal |= LtrConfig->NonSnoopLatencyOverrideValue << 16;
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OvrVal |= LtrConfig->NonSnoopLatencyOverrideMultiplier << 26;
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OvrVal |= B_PCH_PCIE_CFG_LTROVR_LTRNSROVR;
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} else if (LtrConfig->NonSnoopLatencyOverrideMode == 2) {
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if (TreeLtr->MaxNoSnoopLatencyRequirement) {
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OvrEn |= B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN;
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OvrVal |= TreeLtr->MaxNoSnoopLatencyValue << 16;
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OvrVal |= TreeLtr->MaxNoSnoopLatencyScale << 26;
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OvrVal |= B_PCH_PCIE_CFG_LTROVR_LTRNSROVR;
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}
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}
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PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_LTROVR, OvrVal);
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PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_LTROVR2, OvrEn);
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DEBUG ((DEBUG_INFO, "ConfigureRpLtrOverride IsCpuPcie=%d\n", IsCpuPcie));
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DEBUG ((DEBUG_INFO, "ConfigureRpLtrOverride %x Val %x En %x\n", RpBase, OvrVal, OvrEn));
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}
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/**
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This function configures EOI message forwarding for PCIe port.
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If there's an IoAPIC behind this port, forwarding will be enabled
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Otherwise it will be disabled to minimize bus traffic
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@param[in] Segment,Bus,Device,Function address of currently visited PCIe device
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@param[in] IoApicPresent TRUE if there's IoAPIC behind this Root Port
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**/
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VOID
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ConfigureEoiForwarding (
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UINT64 RpBase,
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BOOLEAN IoApicPresent
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)
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{
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UINT32 RpIndex;
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RpIndex = PciePortIndex (RpBase);
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if (IoApicPresent == FALSE) {
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PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_MPC2, B_PCH_PCIE_CFG_MPC2_EOIFD);
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} else {
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///
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/// If there is an IOAPIC discovered behind Root Port, program PSF Multicast registers
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/// in accordance with PCH PCIe BWG PSF EOI Multicast Configuration
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///
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PciSegmentAnd32 (RpBase + R_PCH_PCIE_CFG_MPC2, (UINT32)~B_PCH_PCIE_CFG_MPC2_EOIFD);
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PsfConfigurEoiForPciePort (RpIndex);
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}
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}
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/**
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Configures proprietary parts of L1 substates configuration in Root Port
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@param[in] RpSbdf segment:bus:device:function coordinates of Root Port
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@param[in] LtrCapable TRUE if Root Port is LTR capable
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**/
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VOID
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L1ssProprietaryConfiguration (
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UINT64 RpBase,
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BOOLEAN LtrCapable
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)
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{
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BOOLEAN ClkreqSupported;
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BOOLEAN L1ssEnabled;
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UINT16 PcieCapOffset;
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UINT32 Data32;
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BOOLEAN L1LowSupported;
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ClkreqSupported = PcieIsPhyLanePgEnabled (RpBase);
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PcieCapOffset = PcieBaseFindExtendedCapId (RpBase, V_PCIE_EX_L1S_CID);
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if (PcieCapOffset == 0) {
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L1ssEnabled = FALSE;
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} else {
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Data32 = PciSegmentRead32 (RpBase + PcieCapOffset + R_PCIE_EX_L1SCTL1_OFFSET);
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L1ssEnabled = Data32 & (B_PCIE_EX_L1SCAP_AL1SS | B_PCIE_EX_L1SCAP_AL12S | B_PCIE_EX_L1SCAP_PPL11S |B_PCIE_EX_L1SCAP_PPL12S);
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}
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L1LowSupported = ClkreqSupported && LtrCapable && !L1ssEnabled;
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///
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/// If L1.SNOOZ and L1.OFF (L1 Sub-States) are not supported and per-port CLKREQ# is supported, and LTR is supported:
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/// Enable L1.LOW by setting Dxx:Fn:420[17] = 1b
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///
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if (L1LowSupported) {
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PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL, (UINT32) B_PCH_PCIE_CFG_PCIEPMECTL_L1LE);
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} else {
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PciSegmentAnd32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL, (UINT32) ~B_PCH_PCIE_CFG_PCIEPMECTL_L1LE);
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}
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if (L1LowSupported || L1ssEnabled) {
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///
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/// f. Set Dxx:Fn:420h[0] to 1b prior to L1 enabling if any L1substate is enabled (including L1.LOW)
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///
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PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL, B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE);
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}
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}
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