/** @file
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Header file for PCI Express helpers library
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCI_EXPRESS_HELPERS_LIB_H_
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#define _PCI_EXPRESS_HELPERS_LIB_H_
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#include <PchPolicyCommon.h>
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#include <Library/PcieRpLib.h>
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typedef enum {
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TpoScale2us,
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TpoScale10us,
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TpoScale100us,
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TpoScaleMax
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} T_PO_SCALE;
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//
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// This structure keeps segment:bus:device:function coordinates of a PCIe device
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// in a single variable. PcieCap is offset to PCI Express capabilities.
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//
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typedef struct {
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UINT32 Seg : 8;
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UINT32 Bus : 8;
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UINT32 Dev : 5;
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UINT32 Func : 3;
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UINT32 PcieCap : 8;
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} SBDF;
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/*
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Converts Tpower_on from value:scale notation to microseconds
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@param[in] TpoScale T power on scale
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@param[in] TpoValue T power on value
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@retval number of microseconds
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*/
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UINT32
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TpoToUs (
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UINT32 TpoScale,
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UINT32 TpoValue
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);
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/**
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PCIe controller Sku.
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**/
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typedef enum {
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EnumPchPcie = 0,
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EnumiTbtPcie = 1,
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EnumCpuPcie = 2,
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EnumPciSkuMax = 3
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} PCI_SKU;
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/*
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Initializes the following features in rootport and devices behind it:
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Maximum Payload Size (generic)
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Rootport packet split (proprietary)
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EonOfInterrupt forwarding (proprietary)
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Common Clock Configuration (generic)
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Generic: any code written according to PCIE Express base specification can do that.
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Proprietary: code uses registers and features that are specific to Intel silicon
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and probably only this Reference Code knows how to handle that.
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If OEM implemented generic feature enabling in his platform code or trusts Operating System
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to do it, then those features can be deleted from here.
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CCC requires link retrain, which takes a while. CCC must happen before L0s/L1 programming.
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If there was guarantee no code would access PCI while links retrain, it would be possible to skip this waiting
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@param[in] RpSegment address of rootport on PCIe
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@param[in] RpBus address of rootport on PCIe
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@param[in] RpDevice address of rootport on PCIe
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@param[in] RpFunction address of rootport on PCIe
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@param[in] BusMin minimum Bus number that can be assigned below this rootport
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@param[in] BusMax maximum Bus number that can be assigned below this rootport
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*/
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VOID
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RootportDownstreamConfiguration (
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UINT8 RpSegment,
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UINT8 RpBus,
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UINT8 RpDevice,
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UINT8 RpFunction,
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UINT8 BusMin,
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UINT8 BusMax,
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PCI_SKU PciSku
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);
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/*
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Configures the following power-management related features in rootport and devices behind it:
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LTR limit (generic)
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LTR override (proprietary)
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Clock Power Management (generic)
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L1 substates (generic except for the override table)
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L1.LOW substate (proprietary)
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L0s and L1 (generic)
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Generic: any code written according to PCIE Express base specification can do that.
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Proprietary: code uses registers and features that are specific to Intel silicon
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and probably only this Reference Code knows how to handle that.
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If OEM implemented generic feature enabling in his platform code or trusts Operating System
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to do it, then those features can be deleted from here.
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@param[in] RpSegment address of rootport on PCIe
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@param[in] RpBus address of rootport on PCIe
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@param[in] RpDevice address of rootport on PCIe
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@param[in] RpFunction address of rootport on PCIe
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@param[in] BusMin minimal Bus number that can be assigned below this rootport
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@param[in] BusMax maximum Bus number that can be assigned below this rootport
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@param[in] PcieRpCommonConfig a pointer to Pcie Root Port Common Config
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@param[in] AspmOverrideTableSize size of override array
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@param[in] AspmOverrideTable array of device that need exceptions in configuration
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*/
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VOID
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RootportDownstreamPmConfiguration (
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UINT8 RpSegment,
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UINT8 RpBus,
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UINT8 RpDevice,
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UINT8 RpFunction,
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UINT8 BusMin,
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UINT8 BusMax,
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PCIE_ROOT_PORT_COMMON_CONFIG *PcieRpCommonConfig,
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UINT32 AspmOverrideTableSize,
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PCH_PCIE_DEVICE_OVERRIDE *AspmOverrideTable
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);
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typedef struct {
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UINT32 MaxSnoopLatencyValue : 10;
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UINT32 MaxSnoopLatencyScale : 3;
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UINT32 MaxNoSnoopLatencyValue : 10;
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UINT32 MaxNoSnoopLatencyScale : 3;
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UINT32 Reserved : 6;
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} LTR_LIMIT;
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/**
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Checks if given PCI device is capable of Latency Tolerance Reporting
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@param[in] Sbdf device's segment:bus:device:function coordinates
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@retval TRUE if yes
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**/
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BOOLEAN
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IsLtrCapable (
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SBDF Sbdf
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);
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/**
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Returns combination of two LTR override values
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The resulting LTR override separately chooses stricter limits for snoop and nosnoop
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@param[in] LtrA LTR override values to be combined
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@param[in] LtrB LTR override values to be combined
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@retval LTR override value
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**/
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LTR_OVERRIDE
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CombineLtr (
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LTR_OVERRIDE LtrA,
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LTR_OVERRIDE LtrB
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);
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/**
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Extended Virtual Channel Configuration
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**/
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typedef struct {
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UINT16 CapOffset;
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UINT8 ExtVcCount;
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} MULTI_VC_SUPPORT;
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#endif // _PCI_EXPRESS_HELPERS_LIB_H_
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