/** @file
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PCH DMI library.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchDmiLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Register/PchPcrRegs.h>
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#include <Register/PchDmiRegs.h>
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#include <Register/PchRegsLpc.h>
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#include "PchDmi14.h"
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/**
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This function checks if DMI Secured Register Lock (SRL) is set
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@retval SRL state
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**/
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BOOLEAN
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IsPchDmiLocked (
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VOID
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)
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{
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return IsPchDmi14Locked ();
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}
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/**
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Get PCH TCO base address.
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@retval Address Address of TCO base address.
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**/
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UINT16
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PchDmiGetTcoBase (
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VOID
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)
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{
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//
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// Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
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//
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return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) & B_PCH_DMI_PCR_TCOBASE_TCOBA);
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}
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/**
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Set PCH LPC/eSPI generic IO range decoding in DMI
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@param[in] Address Address for generic IO range base address.
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@param[in] Length Length of generic IO range.
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@param[in] RangeIndex Index of choosen range
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcGenIoRange (
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IN UINT32 Address,
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IN UINT32 Length,
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IN UINT32 RangeIndex
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Set PCH eSPI eSPI CS1# generic IO range decoding in DMI
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@param[in] Address Address for generic IO range base address.
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@param[in] Length Length of generic IO range.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetEspiCs1GenIoRange (
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IN UINT32 Address,
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IN UINT32 Length
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)
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{
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return EFI_UNSUPPORTED;
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}
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/**
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Set PCH LPC/eSPI memory range decoding in DMI
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@param[in] Address Address for memory base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcMemRange (
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IN UINT32 Address
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)
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{
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if (IsPchDmiLocked ()) {
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DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program LPC Memory Range, PCR[DMI] + 2740h to the same value programmed in LPC/eSPI PCI Offset 98h.
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//
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PchPcrWrite32 (
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PID_DMI, R_PCH_DMI_PCR_LPCGMR,
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(Address | B_LPC_CFG_LGMR_LMRD_EN)
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);
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return EFI_SUCCESS;
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}
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/**
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Set PCH eSPI CS1# memory range decoding in DMI
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@param[in] Address Address for memory base address.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetEspiCs1MemRange (
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IN UINT32 Address
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)
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{
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if (IsPchDmiLocked ()) {
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DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// Program LPC Memory Range, PCR[DMI] + 27C0h to the same value programmed in eSPI PCI Offset A8h.
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//
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PchPcrWrite32 (
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PID_DMI, R_PCH_DMI_PCR_SEGMR,
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(Address | B_LPC_CFG_LGMR_LMRD_EN)
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);
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return EFI_SUCCESS;
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}
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/**
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Check if Boot BIOS Strap is set for SPI.
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@retval TRUE Boot BIOS Strap set for SPI
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@retval FALSE Boot BIOS Strap set for LPC/eSPI
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**/
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BOOLEAN
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PchDmiIsBootBiosStrapSetForSpi (
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VOID
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)
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{
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//
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// Check General Control and Status (GCS) [10]
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// '0': SPI
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// '1': LPC/eSPI
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//
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return ((PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_GCS) & B_PCH_DMI_PCR_BBS) != B_PCH_DMI_PCR_BBS);
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}
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/**
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Set PCH BIOS range decoding in DMI
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Please check EDS for detail of BiosDecodeEnable bit definition.
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bit 15: F8-FF Enable
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bit 14: F0-F8 Enable
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bit 13: E8-EF Enable
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bit 12: E0-E8 Enable
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bit 11: D8-DF Enable
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bit 10: D0-D7 Enable
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bit 9: C8-CF Enable
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bit 8: C0-C7 Enable
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bit 7: Legacy F Segment Enable
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bit 6: Legacy E Segment Enable
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bit 5: Reserved
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bit 4: Reserved
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bit 3: 70-7F Enable
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bit 2: 60-6F Enable
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bit 1: 50-5F Enable
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bit 0: 40-4F Enable
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@param[in] BiosDecodeEnable Bios decode enable setting.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetBiosDecodeEnable (
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IN UINT16 BiosDecodeEnable
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)
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{
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC or SPI Offset D8h.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCBDE, BiosDecodeEnable);
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return EFI_SUCCESS;
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}
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/**
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Set PCH LPC/eSPI IO decode ranges in DMI
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Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
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Bit 12: FDD range
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Bit 9:8: LPT range
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Bit 6:4: ComB range
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Bit 2:0: ComA range
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@param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcIoDecodeRanges (
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IN UINT16 LpcIoDecodeRanges
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)
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{
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//
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// This cycle decoding is only allowed to set when DMI is not locked.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);
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return EFI_SUCCESS;
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}
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/**
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Set PCH LPC/eSPI IO enable decoding in DMI
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@param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
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@retval EFI_SUCCESS Successfully completed.
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@retval EFI_UNSUPPORTED DMIC.SRL is set.
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**/
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EFI_STATUS
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PchDmiSetLpcIoEnable (
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IN UINT16 LpcIoEnableDecoding
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)
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{
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//
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// This cycle decoding is only allowed to set when DMI is not locked.
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//
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if (IsPchDmiLocked ()) {
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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//
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// program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h.
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//
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PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);
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return EFI_SUCCESS;
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}
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