/** @file
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This is part of the implementation of an Intel Graphics drivers OpRegion /
|
Software SCI interface between system BIOS, ASL code, and Graphics drivers.
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The code in this file will load the driver and initialize the interface
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/DxeIgdOpRegionInitLib.h>
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#define HEADER_OPREGION_VER_GEN9 0x0200
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#define HEADER_OPREGION_VER_GEN12 0x0201
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GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion;
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/**
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Get VBT data using SaPlaformPolicy
|
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@param[out] VbtFileBuffer Pointer to VBT data buffer.
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@retval EFI_SUCCESS VBT data was returned.
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@retval EFI_NOT_FOUND VBT data not found.
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@exception EFI_UNSUPPORTED Invalid signature in VBT data.
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**/
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EFI_STATUS
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GetIntegratedIntelVbtPtr (
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OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer
|
)
|
{
|
EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS VbtAddress;
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UINT32 Size;
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GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
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SA_POLICY_PROTOCOL *SaPolicy;
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///
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/// Get the SA policy.
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///
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Status = gBS->LocateProtocol (
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&gSaPolicyProtocolGuid,
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NULL,
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(VOID **) &SaPolicy
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
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ASSERT_EFI_ERROR (Status);
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VbtAddress = GraphicsDxeConfig->VbtAddress;
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Size = GraphicsDxeConfig->Size;
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if (VbtAddress == 0x00000000) {
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return EFI_NOT_FOUND;
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} else {
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///
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/// Check VBT signature
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///
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*VbtFileBuffer = NULL;
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*VbtFileBuffer = (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;
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if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) != VBT_SIGNATURE) {
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FreePool (*VbtFileBuffer);
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*VbtFileBuffer = NULL;
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return EFI_UNSUPPORTED;
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}
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}
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if (Size == 0) {
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return EFI_NOT_FOUND;
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} else {
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///
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/// Check VBT size
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///
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if ((*VbtFileBuffer)->HeaderVbtSize > Size) {
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(*VbtFileBuffer)->HeaderVbtSize = (UINT16) Size;
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}
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}
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return EFI_SUCCESS;
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}
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/**
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Get a pointer to an uncompressed image of the Intel video BIOS.
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@Note: This function would only be called if the video BIOS at 0xC000 is
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missing or not an Intel video BIOS. It may not be an Intel video BIOS
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if the Intel graphic contoller is considered a secondary adapter.
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@param[out] VBiosImage - Pointer to an uncompressed Intel video BIOS. This pointer must
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be set to NULL if an uncompressed image of the Intel Video BIOS
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is not obtainable.
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@retval EFI_SUCCESS - VBiosPtr is updated.
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@exception EFI_UNSUPPORTED - No Intel video BIOS found.
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**/
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EFI_STATUS
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GetIntegratedIntelVBiosPtr (
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OUT INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage
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)
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{
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EFI_HANDLE *HandleBuffer;
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UINTN HandleCount;
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UINTN Index;
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INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr;
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EFI_STATUS Status;
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EFI_PCI_IO_PROTOCOL *PciIo;
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INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage;
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///
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/// Set as if an umcompressed Intel video BIOS image was not obtainable.
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///
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VBiosRomImage = NULL;
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///
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/// Get all PCI IO protocols
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///
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Status = gBS->LocateHandleBuffer (
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ByProtocol,
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&gEfiPciIoProtocolGuid,
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NULL,
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&HandleCount,
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&HandleBuffer
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);
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ASSERT_EFI_ERROR (Status);
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///
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/// Find the video BIOS by checking each PCI IO handle for an Intel video
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/// BIOS OPROM.
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///
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for (Index = 0; Index < HandleCount; Index++) {
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Status = gBS->HandleProtocol (
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HandleBuffer[Index],
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&gEfiPciIoProtocolGuid,
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(VOID **) &PciIo
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);
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ASSERT_EFI_ERROR (Status);
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VBiosRomImage = PciIo->RomImage;
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///
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/// If this PCI device doesn't have a ROM image, skip to the next device.
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///
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if (!VBiosRomImage) {
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continue;
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}
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///
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/// Get pointer to PCIR structure
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///
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PcirBlockPtr = (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosRomImage + VBiosRomImage->PcirOffset);
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///
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/// Check if we have an Intel video BIOS OPROM.
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///
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if ((VBiosRomImage->Signature == OPTION_ROM_SIGNATURE) &&
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(PcirBlockPtr->VendorId == V_SA_MC_VID) &&
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(PcirBlockPtr->ClassCode[0] == 0x00) &&
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(PcirBlockPtr->ClassCode[1] == 0x00) &&
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(PcirBlockPtr->ClassCode[2] == 0x03)
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) {
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///
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/// Found Intel video BIOS.
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///
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*VBiosImage = VBiosRomImage;
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return EFI_SUCCESS;
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}
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}
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///
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/// No Intel video BIOS found.
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///
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///
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/// Free any allocated buffers
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///
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FreePool (HandleBuffer);
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return EFI_UNSUPPORTED;
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}
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/**
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Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).
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The VBT (Video BIOS Table) is a block of customizable data that is built
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within the video BIOS and edited by customers.
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@retval EFI_SUCCESS - Video BIOS VBT information returned.
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@exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosVbtPtr = NULL).
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**/
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EFI_STATUS
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GetVBiosVbtEndOfDxe (
|
VOID
|
)
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{
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INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr;
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VBIOS_VBT_STRUCTURE *VBiosVbtPtr;
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EFI_STATUS Status;
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VBIOS_VBT_STRUCTURE *VbtFileBuffer;
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GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
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SA_POLICY_PROTOCOL *SaPolicy;
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VbtFileBuffer = NULL;
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///
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/// Get the SA policy.
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///
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Status = gBS->LocateProtocol (
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&gSaPolicyProtocolGuid,
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NULL,
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(VOID **) &SaPolicy
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
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ASSERT_EFI_ERROR (Status);
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VBiosPtr = NULL;
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///
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/// Try to get VBT from FV.
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///
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GetIntegratedIntelVbtPtr (&VbtFileBuffer);
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if (VbtFileBuffer != NULL) {
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///
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/// Video BIOS not found, use VBT from SaPolicy
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///
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DEBUG ((DEBUG_INFO, "VBT data found\n"));
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CopyMem (mIgdOpRegion.OpRegion->Header.DVER, GraphicsDxeConfig->GopVersion, sizeof(GraphicsDxeConfig->GopVersion));
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mIgdOpRegion.OpRegion->MBox3.RVDA = 0;
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mIgdOpRegion.OpRegion->MBox3.RVDS = 0;
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if ((VbtFileBuffer->HeaderVbtSize > 0x1800)) { // VBT > 6KB
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DEBUG ((DEBUG_INFO, "Extended VBT supported\n"));
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mIgdOpRegion.OpRegion->MBox3.RVDA = sizeof (IGD_OPREGION_STRUCTURE); // Relative offset at the end of Op-region.
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mIgdOpRegion.OpRegion->MBox3.RVDS = ((VbtFileBuffer->HeaderVbtSize) & (UINT32)~(0x1FF)) + 0x200; // Aligned VBT Data Size to 512 bytes.
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CopyMem ((CHAR8 *)(UINTN)(mIgdOpRegion.OpRegion) + sizeof (IGD_OPREGION_STRUCTURE), VbtFileBuffer, mIgdOpRegion.OpRegion->MBox3.RVDS);
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} else {
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CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VbtFileBuffer, VbtFileBuffer->HeaderVbtSize);
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}
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return EFI_SUCCESS;
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}
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if (VBiosPtr == NULL) {
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return EFI_UNSUPPORTED;
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}
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DEBUG ((DEBUG_INFO, "VBIOS found at 0x%X\n", VBiosPtr));
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VBiosVbtPtr = (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->VbtOffset);
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if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) != VBT_SIGNATURE) {
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return EFI_UNSUPPORTED;
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}
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///
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/// Initialize Video BIOS version with its build number.
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///
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mIgdOpRegion.OpRegion->Header.VVER[0] = VBiosVbtPtr->CoreBlockBiosBuild[0];
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mIgdOpRegion.OpRegion->Header.VVER[1] = VBiosVbtPtr->CoreBlockBiosBuild[1];
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mIgdOpRegion.OpRegion->Header.VVER[2] = VBiosVbtPtr->CoreBlockBiosBuild[2];
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mIgdOpRegion.OpRegion->Header.VVER[3] = VBiosVbtPtr->CoreBlockBiosBuild[3];
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CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VBiosVbtPtr, VBiosVbtPtr->HeaderVbtSize);
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///
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/// Return final status
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///
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return EFI_SUCCESS;
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}
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/**
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Graphics OpRegion / Software SCI driver installation function.
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@param[in] void - None
|
@retval EFI_SUCCESS - The driver installed without error.
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@retval EFI_ABORTED - The driver encountered an error and could not complete
|
installation of the ACPI tables.
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**/
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EFI_STATUS
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IgdOpRegionInit (
|
VOID
|
)
|
{
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EFI_HANDLE Handle;
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EFI_STATUS Status;
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UINT32 DwordData;
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UINT64 IgdBaseAddress;
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SA_POLICY_PROTOCOL *SaPolicy;
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GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
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UINT8 Index;
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SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol;
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VBIOS_VBT_STRUCTURE *VbtFileBuffer;
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UINT16 ExtendedVbtSize;
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///
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/// Get the SA policy.
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///
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Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **)&SaPolicy);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
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ASSERT_EFI_ERROR (Status);
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VbtFileBuffer = NULL;
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ExtendedVbtSize = 0;
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GetIntegratedIntelVbtPtr (&VbtFileBuffer);
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///
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/// Locate the SA Global NVS Protocol.
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///
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Status = gBS->LocateProtocol (
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&gSaNvsAreaProtocolGuid,
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NULL,
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(VOID **) &SaNvsAreaProtocol
|
);
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ASSERT_EFI_ERROR (Status);
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///
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/// Check if VBT size is >6KB then allocate an ACPI NVS memory buffer as the IGD OpRegion + extended VBT size,
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/// zero initialize it, and set the IGD OpRegion pointer in the Global NVS area structure.
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///
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if ((VbtFileBuffer != NULL) && (VbtFileBuffer->HeaderVbtSize > 0x1800)) {
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ExtendedVbtSize = ((VbtFileBuffer->HeaderVbtSize) & (UINT32)~(0x1FF)) + 0x200;
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}
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Status = (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (IGD_OPREGION_STRUCTURE) + ExtendedVbtSize, (VOID **) &mIgdOpRegion.OpRegion);
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ASSERT_EFI_ERROR (Status);
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SetMem (mIgdOpRegion.OpRegion, sizeof (IGD_OPREGION_STRUCTURE) + ExtendedVbtSize, 0);
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SaNvsAreaProtocol->Area->IgdOpRegionAddress = (UINT32) (UINTN) (mIgdOpRegion.OpRegion);
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///
|
/// If IGD is disabled return
|
///
|
IgdBaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD_DEV_NUM, IGD_FUN_NUM, 0);
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if (PciSegmentRead32 (IgdBaseAddress + 0) == 0xFFFFFFFF) {
|
return EFI_SUCCESS;
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}
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///
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/// Initialize OpRegion Header
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///
|
CopyMem (mIgdOpRegion.OpRegion->Header.SIGN, HEADER_SIGNATURE, sizeof (HEADER_SIGNATURE));
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///
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/// Set OpRegion Size in KBs
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///
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mIgdOpRegion.OpRegion->Header.SIZE = HEADER_SIZE / 1024;
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mIgdOpRegion.OpRegion->Header.OVER = (UINT32) (LShiftU64 (HEADER_OPREGION_VER_GEN12, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));
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///
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/// All Mailboxes are supported.
|
///
|
mIgdOpRegion.OpRegion->Header.MBOX = HEADER_MBOX_SUPPORT;
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|
///
|
/// Initialize OpRegion Mailbox 1 (Public ACPI Methods).
|
///
|
/// Note - The initial setting of mailbox 1 fields is implementation specific.
|
/// Adjust them as needed many even coming from user setting in setup.
|
///
|
///
|
/// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation).
|
///
|
/// Note - The initial setting of mailbox 3 fields is implementation specific.
|
/// Adjust them as needed many even coming from user setting in setup.
|
///
|
///
|
/// Do not initialize TCHE. This field is written by the graphics driver only.
|
///
|
///
|
/// The ALSI field is generally initialized by ASL code by reading the embedded controller.
|
///
|
mIgdOpRegion.OpRegion->Header.PCON = GraphicsDxeConfig->PlatformConfig;
|
mIgdOpRegion.OpRegion->Header.PCON = mIgdOpRegion.OpRegion->Header.PCON | 0x2;
|
|
mIgdOpRegion.OpRegion->MBox3.BCLP = BACKLIGHT_BRIGHTNESS;
|
|
mIgdOpRegion.OpRegion->MBox3.PFIT = (FIELD_VALID_BIT | PFIT_STRETCH);
|
|
///
|
/// Reporting to driver for VR IMON Calibration. Bits [5-1] values supported 14A to 31A.
|
///
|
mIgdOpRegion.OpRegion->MBox3.PCFT = (SaNvsAreaProtocol->Area->GfxTurboIMON << 1) & 0x003E;
|
|
///
|
/// Set Initial current Brightness
|
///
|
mIgdOpRegion.OpRegion->MBox3.CBLV = (INIT_BRIGHT_LEVEL | FIELD_VALID_BIT);
|
|
///
|
/// Static Backlight Brightness Level Duty cycle Mapping Table
|
///
|
for (Index = 0; Index < MAX_BCLM_ENTRIES; Index++) {
|
mIgdOpRegion.OpRegion->MBox3.BCLM[Index] = GraphicsDxeConfig->BCLM[Index];
|
}
|
|
mIgdOpRegion.OpRegion->MBox3.IUER = 0x00;
|
|
if (!EFI_ERROR (Status)) {
|
mIgdOpRegion.OpRegion->MBox3.IUER = GraphicsDxeConfig->IuerStatusVal;
|
}
|
|
///
|
/// Initialize hardware state:
|
/// Set ASLS Register to the OpRegion physical memory address.
|
/// Set SWSCI register bit 15 to a "1" to activate SCI interrupts.
|
///
|
PciSegmentWrite32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET, (UINT32) (UINTN) (mIgdOpRegion.OpRegion));
|
PciSegmentAndThenOr16 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET, (UINT16) ~(BIT0), BIT15);
|
|
DwordData = PciSegmentRead32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET);
|
S3BootScriptSaveMemWrite (
|
S3BootScriptWidthUint32,
|
(UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET),
|
1,
|
&DwordData
|
);
|
DwordData = PciSegmentRead32 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET);
|
S3BootScriptSaveMemWrite (
|
S3BootScriptWidthUint32,
|
(UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET),
|
1,
|
&DwordData
|
);
|
|
///
|
/// Install OpRegion / Software SCI protocol
|
///
|
Handle = NULL;
|
Status = gBS->InstallMultipleProtocolInterfaces (
|
&Handle,
|
&gIgdOpRegionProtocolGuid,
|
&mIgdOpRegion,
|
NULL
|
);
|
ASSERT_EFI_ERROR (Status);
|
|
///
|
/// Return final status
|
///
|
return EFI_SUCCESS;
|
}
|
|
/**
|
Update Graphics OpRegion after PCI enumeration.
|
|
@param[in] void - None
|
@retval EFI_SUCCESS - The function completed successfully.
|
**/
|
EFI_STATUS
|
UpdateIgdOpRegionEndOfDxe (
|
VOID
|
)
|
{
|
EFI_STATUS Status;
|
UINTN HandleCount;
|
EFI_HANDLE *HandleBuffer;
|
UINTN Index;
|
EFI_PCI_IO_PROTOCOL *PciIo;
|
PCI_TYPE00 Pci;
|
UINTN Segment;
|
UINTN Bus;
|
UINTN Device;
|
UINTN Function;
|
|
Bus = 0;
|
Device = 0;
|
Function = 0;
|
|
DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));
|
|
mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx Adapter field is valid
|
mIgdOpRegion.OpRegion->Header.PCON &= (UINT32) (~BIT7); //Assume No External Gfx Adapter
|
|
///
|
/// Get all PCI IO protocols handles
|
///
|
Status = gBS->LocateHandleBuffer (
|
ByProtocol,
|
&gEfiPciIoProtocolGuid,
|
NULL,
|
&HandleCount,
|
&HandleBuffer
|
);
|
|
if (!EFI_ERROR (Status)) {
|
for (Index = 0; Index < HandleCount; Index++) {
|
///
|
/// Get the PCI IO Protocol Interface corresponding to each handle
|
///
|
Status = gBS->HandleProtocol (
|
HandleBuffer[Index],
|
&gEfiPciIoProtocolGuid,
|
(VOID **) &PciIo
|
);
|
|
if (!EFI_ERROR (Status)) {
|
///
|
/// Read the PCI configuration space
|
///
|
Status = PciIo->Pci.Read (
|
PciIo,
|
EfiPciIoWidthUint32,
|
0,
|
sizeof (Pci) / sizeof (UINT32),
|
&Pci
|
);
|
|
///
|
/// Find the display controllers devices
|
///
|
if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
|
Status = PciIo->GetLocation (
|
PciIo,
|
&Segment,
|
&Bus,
|
&Device,
|
&Function
|
);
|
|
//
|
// Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
|
//
|
if (!EFI_ERROR (Status) && (Bus > 0)) {
|
//External Gfx Adapter Detected and Available
|
DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
|
mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
|
break;
|
}
|
}
|
}
|
}
|
}
|
|
///
|
/// Free any allocated buffers
|
///
|
if (HandleBuffer != NULL) {
|
FreePool (HandleBuffer);
|
}
|
|
///
|
/// Return final status
|
///
|
return Status;
|
}
|
