/** @file
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Header file for GbeMdiLib.
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Conventions:
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- Prefixes:
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Definitions beginning with "R_" are registers
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Definitions beginning with "B_" are bits within registers
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Definitions beginning with "V_" are meaningful values within the bits
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Definitions beginning with "S_" are register sizes
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Definitions beginning with "N_" are the bit position
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- In general, PCH registers are denoted by "_PCH_" in register names
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- Registers / bits that are different between PCH generations are denoted by
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"_PCH_[generation_name]_" in register/bit names.
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- Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
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Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
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e.g., "_PCH_LP_"
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Registers / bits names without or _LP_ apply for LP.
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- Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
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at the end of the register/bit names
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- Registers / bits of new devices introduced in a PCH generation will be just named
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as "_PCH_" without [generation_name] inserted.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _GBE_MDI_LIB_H_
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#define _GBE_MDI_LIB_H_
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//
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// Maximum loop time for GbE status check
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// 4000 * 50 = 200 mSec in total
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//
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#define GBE_MAX_LOOP_TIME 4000
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#define GBE_ACQUIRE_MDIO_DELAY 50
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#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting page
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//
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// LAN PHY MDI settings
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//
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// MDI Control Register Bits
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// 31:30 Reserved
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// This field is reserved and returns 0.
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// 29 Interrupt Enable.
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// When this bit is set to 1 by software, it causes the device to assert
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// an interrupt indicating the end of an MDI cycle.
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// 28 Ready.
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// Set to 1 by the device at the end of MDI transaction (i.e., indicates a Read or
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// Write has been completed. It should be reset to 0 by software at the same time the
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// command is written.
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// 27:26 Opcode
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// For an MDI write, the opcode equals 01b, and for MDI read, 10b. 00b and
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// 11b are reserved and should not be used.
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// 25:21 PHYAdd
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// PHY Address
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// 20:16 RegAdd
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// PHY Register Address
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// 15:0 Data
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#define B_PHY_MDI_READY BIT28
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#define B_PHY_MDI_READ BIT27
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#define B_PHY_MDI_WRITE BIT26
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//
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// PHY SPECIFIC registers
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//
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#define B_PHY_MDI_PHY_ADDRESS_02 BIT22
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//
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// PHY GENERAL registers
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// Registers 0 to 15 are defined by the specification
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// Registers 16 to 31 are left available to the vendor
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//
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#define B_PHY_MDI_PHY_ADDRESS_01 BIT21
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#define B_PHY_MDI_PHY_ADDRESS_MASK (BIT25 | BIT24 | BIT23 | BIT22 | BIT21)
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//
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// PHY Identifier Register 2
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// Bits [15:10] - PHY ID Number - The PHY identifier composed of bits 3 through 18
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// of the Organizationally Unique Identifier (OUI)
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// Bits [9:4] - Device Model Number
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// Bits [3:0] - Device Revision Number
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//
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#define R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2 0x00030000
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#define MDI_REG_SHIFT(x) (x << 16)
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#define B_PHY_MDI_PHY_REGISTER_MASK (BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
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#define R_PHY_MDI_PHY_REG_SET_ADDRESS 0x00110000 // Used after new page setting
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#define R_PHY_MDI_PHY_REG_DATA_READ_WRITE 0x00120000
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#define R_PHY_MDI_PHY_REG_SET_PAGE 0x001F0000
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//
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// LAN PHY MDI registers and bits
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//
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//
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// Page 769 Port Control Registers
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// 6020h (769 * 32)
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//
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#define PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS 769
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//
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// Custom Mode Control PHY Address 01, Page 769, Register 16
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//
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#define R_PHY_MDI_PAGE_769_REGISETER_16_CMC 0x0010
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//
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// Custom Mode Control
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// Page 769, Register 16, BIT 10
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// 0 - normal MDIO frequency access
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// 1 - reduced MDIO frequency access (slow mdio)
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// required for read during cable disconnect
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//
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#define B_PHY_MDI_PAGE_769_REGISETER_16_CMC_MDIO_FREQ_ACCESS BIT10
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//
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// Port General Configuration PHY Address 01, Page 769, Register 17
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//
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#define R_PHY_MDI_PAGE_769_REGISETER_17_PGC 0x0011
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//
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// Page 769, Register 17, BIT 4
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// Enables host wake up
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//
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#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP BIT4
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//
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// Page 769, Register 17, BIT 2
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// Globally enable the MAC power down feature while the
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// GbE supports WoL. When set to 1b,
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// pages 800 and 801 are enabled for
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// configuration and Host_WU_Active is not blocked for writes.
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//
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#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE BIT2
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//
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// Page 800 Wake Up Registers
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// 6400h (800 * 32)
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//
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#define PHY_MDI_PAGE_800_WAKE_UP_REGISTERS 800
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//
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// Wake Up Control - WUC PHY Address 01, Page 800, Register 1
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// 1h (Register 1)
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//
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#define R_PHY_MDI_PAGE_800_REGISETER_1_WUC 0x0001
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//
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// Wake Up Control - (WUC)
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// Page 800, Register 1, BIT 0
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// Advance Power Management Enable (APME)
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// If set to 1b, APM wake up is enabled.
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//
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#define B_PHY_MDI_PAGE_800_REGISETER_1_WUC_APME BIT0
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//
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// Receive Address Low - RAL PHY Address 01, Page 800, Register 16
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// 10h (Register 16)
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//
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#define R_PHY_MDI_PAGE_800_REGISETER_16_RAL0 0x0010
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//
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// Receive Address Low - RAL PHY Address 01, Page 800, Register 17
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// 11h (Register 17)
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//
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#define R_PHY_MDI_PAGE_800_REGISETER_17_RAL1 0x0011
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//
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// Receive Address High - RAH PHY Address 01, Page 800, Register 18
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// 12h (Register 18)
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//
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#define R_PHY_MDI_PAGE_800_REGISETER_18_RAH0 0x0012
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//
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// Receive Address High - RAH PHY Address 01, Page 800, Register 19
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// 13h (Register 19)
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//
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#define R_PHY_MDI_PAGE_800_REGISETER_19_RAH1 0x0013
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//
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// Setting AV (BIT15 RAH is divided on two registers)
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// RAH Register 19, Page 800, BIT 31
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//
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// Address valid (AV)
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// When this bit is set, the relevant RAL and RAH are valid
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//
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#define B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID BIT15
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//
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// Page 803 Host WoL Packet
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// 6460h (803 * 32)
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//
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#define PHY_MDI_PAGE_803_HOST_WOL_PACKET 803
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//
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// Host WoL Packet Clear - HWPC PHY Address 01, Page 803, Register 66
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//
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#define R_PHY_MDI_PAGE_803_REGISETER_66_HWPC 0x0042
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/**
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Change Extended Device Control Register BIT 11 to 1 which
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forces the interface between the MAC and the Phy to be on SMBus.
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Cleared on the assertion of PCI reset.
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@param [in] GbeBar GbE MMIO space
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**/
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VOID
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GbeMdiForceMACtoSMB (
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IN UINT32 GbeBar
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);
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/**
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Test for MDIO operation complete.
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@param [in] GbeBar GbE MMIO space
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@retval EFI_SUCCESS
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@retval EFI_TIMEOUT
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**/
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EFI_STATUS
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GbeMdiWaitReady (
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IN UINT32 GbeBar
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);
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/**
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Acquire MDIO software semaphore.
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1. Ensure that MBARA offset F00h [5] = 1b
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2. Poll MBARA offset F00h [5] up to 200ms
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@param [in] GbeBar GbE MMIO space
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@retval EFI_SUCCESS
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@retval EFI_TIMEOUT
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**/
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EFI_STATUS
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GbeMdiAcquireMdio (
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IN UINT32 GbeBar
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);
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/**
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Release MDIO software semaphore by clearing MBARA offset F00h [5]
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@param [in] GbeBar GbE MMIO space
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**/
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VOID
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GbeMdiReleaseMdio (
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IN UINT32 GbeBar
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);
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/**
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Sets page on MDI
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Page setting is attempted twice.
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If first attempt failes MAC and the Phy are force to be on SMBus
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@param [in] GbeBar GbE MMIO space
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@param [in] Data Value to write in lower 16bits.
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@retval EFI_SUCCESS Page setting was successfull
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@retval EFI_DEVICE_ERROR Returned if both attermps of setting page failed
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**/
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EFI_STATUS
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GbeMdiSetPage (
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IN UINT32 GbeBar,
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IN UINT32 Page
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);
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/**
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Sets Register in current page.
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@param [in] GbeBar GbE MMIO space
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@param [in] register Register number
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@return EFI_STATUS
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**/
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EFI_STATUS
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GbeMdiSetRegister (
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IN UINT32 GbeBar,
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IN UINT32 Register
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);
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/**
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Perform MDI read.
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@param [in] GbeBar GbE MMIO space
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@param [in] PhyAddress Phy Address General - 02 or Specific - 01
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@param [in] PhyRegister Phy Register
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@param [out] ReadData Return Value
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@retval EFI_SUCCESS Based on response from GbeMdiWaitReady
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@retval EFI_TIMEOUT Based on response from GbeMdiWaitReady
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@retval EFI_INVALID_PARAMETER If Phy Address or Register validaton failed
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**/
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EFI_STATUS
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GbeMdiRead (
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IN UINT32 GbeBar,
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IN UINT32 PhyAddress,
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IN UINT32 PhyRegister,
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OUT UINT16 *ReadData
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);
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/**
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Perform MDI write.
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@param [in] GbeBar GbE MMIO space
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@param [in] PhyAddress Phy Address General - 02 or Specific - 01
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@param [in] PhyRegister Phy Register
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@param [in] WriteData Value to write in lower 16bits.
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@retval EFI_SUCCESS Based on response from GbeMdiWaitReady
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@retval EFI_TIMEOUT Based on response from GbeMdiWaitReady
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@retval EFI_INVALID_PARAMETER If Phy Address or Register validaton failed
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**/
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EFI_STATUS
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GbeMdiWrite (
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IN UINT32 GbeBar,
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IN UINT32 PhyAddress,
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IN UINT32 PhyRegister,
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IN UINT32 WriteData
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);
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/**
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Gets Phy Revision and Model Number
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from PHY IDENTIFIER register 2 (offset 3)
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@param [in] GbeBar GbE MMIO space
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@param [out] LanPhyRevision Return Value
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@return EFI_STATUS
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@return EFI_INVALID_PARAMETER When GbeBar is incorrect
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**/
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EFI_STATUS
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GbeMdiGetLanPhyRevision (
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IN UINT32 GbeBar,
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OUT UINT16 *LanPhyRevision
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);
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#endif // _GBE_MDI_LIB_H_
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