/** @file
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Header file for PchPcieRpLib.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PCIERP_LIB_H_
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#define _PCH_PCIERP_LIB_H_
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#include <Library/PchPcrLib.h>
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/**
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PCIe controller bifurcation configuration.
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**/
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typedef enum {
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PcieBifurcationDefault = 0,
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PcieBifurcation4x1,
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PcieBifurcation1x2_2x1,
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PcieBifurcation2x2,
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PcieBifurcation1x4,
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PcieBifurcation4x2,
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PcieBifurcation1x4_2x2,
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PcieBifurcation2x2_1x4,
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PcieBifurcation2x4,
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PcieBifurcation1x8,
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PcieBifurcationUnknown,
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PcieBifurcationMax
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} PCIE_BIFURCATION_CONFIG;
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/**
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This function returns PID according to PCIe controller index
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@param[in] ControllerIndex PCIe controller index
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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PchGetPcieControllerSbiPid (
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IN UINT32 ControllerIndex
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);
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/**
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This function returns PID according to Root Port Number
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@param[in] RpIndex Root Port Index (0-based)
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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GetRpSbiPid (
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IN UINTN RpIndex
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);
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/**
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Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
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@param[in] RpNumber Root port physical number. (0-based)
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@param[out] RpDev Return corresponding root port device number.
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@param[out] RpFun Return corresponding root port function number.
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@retval EFI_SUCCESS
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**/
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EFI_STATUS
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EFIAPI
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GetPchPcieRpDevFun (
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IN UINTN RpNumber,
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OUT UINTN *RpDev,
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OUT UINTN *RpFun
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);
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/**
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Get Root Port physical Number by Pch Pcie Root Port Device and Function Number
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@param[in] RpDev Root port device number.
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@param[in] RpFun Root port function number.
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@param[out] RpNumber Return corresponding physical Root Port index (0-based)
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@retval EFI_SUCCESS Physical root port is retrieved
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@retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid
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@retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port
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**/
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EFI_STATUS
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EFIAPI
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GetPchPcieRpNumber (
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IN UINTN RpDev,
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IN UINTN RpFun,
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OUT UINTN *RpNumber
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);
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/**
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Gets pci segment base address of PCIe root port.
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@param RpIndex Root Port Index (0 based)
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@return PCIe port base address.
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**/
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UINT64
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PchPcieBase (
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IN UINT32 RpIndex
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);
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/**
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Determines whether L0s is supported on current stepping.
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@return TRUE if L0s is supported, FALSE otherwise
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**/
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BOOLEAN
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PchIsPcieL0sSupported (
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VOID
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);
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/**
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Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
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- RxL0s exit causes recovery
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- Disabling PCIe L0s capability disables L1
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Use this function to determine affected steppings.
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@return TRUE if Native ASPM is supported, FALSE otherwise
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**/
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BOOLEAN
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PchIsPcieNativeAspmSupported (
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VOID
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);
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#endif // _PCH_PCIERP_LIB_H_
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