/** @file
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DMI policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_DMI_CONFIG_H_
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#define _PCH_DMI_CONFIG_H_
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#define PCH_DMI_CONFIG_REVISION 2
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extern EFI_GUID gPchDmiConfigGuid;
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#pragma pack (push,1)
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/**
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The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Add OpioRecenter
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
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UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
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UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
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UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
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/**
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When set to TRUE turns on:
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- L1 State Controller Power Gating
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- L1 State PHY Data Lane Power Gating
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- PHY Common Lane Power Gating
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- Hardware Autonomous Enable
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- PMC Request Enable and Sleep Enable
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**/
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UINT32 DmiPowerReduction : 1;
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UINT32 OpioRecenter : 1; ///< 0: Disable; <b>1: Enable</b> Opio Recentering Disable for Pcie latency
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UINT32 Rsvdbits : 19; ///< Reserved bits
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} PCH_DMI_CONFIG;
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#pragma pack (pop)
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#endif // _PCH_DMI_CONFIG_H_
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