/** @file
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PCH FIVR policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _FIVR_CONFIG_H_
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#define _FIVR_CONFIG_H_
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#define FIVR_CONFIG_REVISION 1
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extern EFI_GUID gFivrConfigGuid;
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#pragma pack (push,1)
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/**
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Rail support in S0ix and Sx
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Settings other than FivrRailDisabled can be OR'ed
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**/
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typedef enum {
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FivrRailDisabled = 0,
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FivrRailInS0i1S0i2 = BIT0,
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FivrRailInS0i3 = BIT1,
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FivrRailInS3 = BIT2,
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FivrRailInS4 = BIT3,
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FivrRailInS5 = BIT4,
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FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
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FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
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FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
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} FIVR_RAIL_SX_STATE;
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typedef enum {
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FivrRetentionActive = BIT0,
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FivrNormActive = BIT1,
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FivrMinActive = BIT2,
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FivrMinRetention = BIT3
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} FIVR_RAIL_SUPPORTED_VOLTAGE;
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/**
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Structure for V1p05/Vnn VR rail configuration
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**/
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typedef struct {
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/**
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Mask to enable the usage of external VR rail in specific S0ix or Sx states
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Use values from FIVR_RAIL_SX_STATE
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The default is <b>FivrRailDisabled</b>.
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**/
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UINT32 EnabledStates : 5;
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/**
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VR rail voltage value that will be used in S0i2/S0i3 states.
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This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
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The default for Vnn is set to <b>420 - 1050 mV</b>.
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**/
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UINT32 Voltage : 11;
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/**
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@deprecated
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THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
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VR rail Icc Max Value
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Granularity of this setting is 1mA and maximal possible value is 500mA
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The default is <b> 0mA </b>.
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**/
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UINT32 IccMax : 8;
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/**
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This register holds the control hold off values to be used when
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changing the rail control for external bypass value in us
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**/
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UINT32 CtrlRampTmr : 8;
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/**
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Mask to set the supported configuration in VR rail.
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Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
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**/
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UINT32 SupportedVoltageStates : 4;
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/**
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VR rail Icc Maximum Value
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Granularity of this setting is 1mA and maximal possible value is 500mA
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The default is <b> 0mA </b>.
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**/
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UINT32 IccMaximum : 16;
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UINT32 RsvdBits1 : 12;
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} FIVR_EXT_RAIL_CONFIG;
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/**
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Structure for VCCIN_AUX voltage rail configuration
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**/
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typedef struct {
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/**
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Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
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Voltage transition time required by motherboard voltage regulator when PCH changes
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the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
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This field has 1us resolution.
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When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
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The default is <b> 0xC </b>.
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**/
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UINT8 LowToHighCurModeVolTranTime;
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/**
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Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
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Voltage transition time required by motherboard voltage regulator when PCH changes
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the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
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This field has 1us resolution.
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When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
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The default is <b> 0x36 </b>.
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**/
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UINT8 RetToHighCurModeVolTranTime;
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/**
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Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
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Voltage transition time required by motherboard voltage regulator when PCH changes
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the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
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This field has 1us resolution.
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When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
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The default is <b> 0x2B </b>.
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**/
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UINT8 RetToLowCurModeVolTranTime;
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UINT8 RsvdByte1;
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/**
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Transition time in microseconds from Off (0V) to High Current Mode Voltage.
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Voltage transition time required by motherboard voltage regulator when PCH changes
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the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
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This field has 1us resolution.
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0 = Transition to 0V is disabled
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Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
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in all S0 & Sx power states after initial start up on G3 exit
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The default is <b> 0x96 </b>.
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**/
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UINT32 OffToHighCurModeVolTranTime : 11;
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UINT32 RsvdBits1 : 21;
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} FIVR_VCCIN_AUX_CONFIG;
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/**
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The PCH_FIVR_CONFIG block describes FIVR settings.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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External V1P05 VR rail configuration.
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**/
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FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
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/**
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External Vnn VR rail configuration.
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**/
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FIVR_EXT_RAIL_CONFIG ExtVnnRail;
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/**
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Additional External Vnn VR rail configuration that will get applied
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in Sx entry SMI callback. Required only if External Vnn VR
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needs different settings for Sx than those specified in ExtVnnRail.
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**/
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FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
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/**
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VCCIN_AUX voltage rail configuration.
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**/
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FIVR_VCCIN_AUX_CONFIG VccinAux;
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/**
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Enable/Disable FIVR Dynamic Power Management
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Default is <b> 1 </b>.
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**/
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UINT32 FivrDynPm : 1;
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UINT32 RsvdBits2 : 31;
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} PCH_FIVR_CONFIG;
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#pragma pack (pop)
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#endif // _FIVR_CONFIG_H_
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