/** @file
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Pcie root port policy
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_PCIE_CONFIG_H_
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#define _CPU_PCIE_CONFIG_H_
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#include <Library/GpioLib.h>
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#include <Library/CpuPcieInfoFruLib.h>
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#include <PcieConfig.h>
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#include <ConfigBlock.h>
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#include <Register/SaRegsHostBridge.h>
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#pragma pack(push, 1)
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#define CPU_PCIE_PEI_PREMEM_CONFIG_REVISION 1
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#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 4
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/**
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Making any setup structure change after code frozen
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will need to maintain backward compatibility, bump up
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structure revision and update below history table\n
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Add Gen3TxOverride and Gen4TxOverride
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<b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
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<b>Revision 4</b>: - Add FOMS Control Policy Setup Variable
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<b>Revision 5</b>: - Add Gen3HwEqOverride and Gen4HwEqOverride
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<b>Revision 6</b>: - Align revision with CPU_PCIE_RP_CONFIG_REVISION value
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**/
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#define CPU_PCIE_RP_CONFIG_REVISION 6
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#define L0_SET BIT0
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#define L1_SET BIT1
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/**
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PCI Express and DMI controller configuration\n
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@note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
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<b>Revision 1</b>:
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- Initial version.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
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/**
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Offset 28:0 :
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<b>(Test)</b> DMI Link Speed Control
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- <b>Auto</b> (0x0) : Maximum possible link speed (Default)
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- Gen1 (0x1) : Limit Link to Gen1 Speed
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- Gen2 (0x2) : Limit Link to Gen2 Speed
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- Gen3 (0x3) : Limit Link to Gen3 Speed
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**/
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UINT32 DmiMaxLinkSpeed : 2;
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/**
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Offset 28:2 :
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<b>(Test)</b> DMI Equalization Phase 2 Enable Control
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- Disabled (0x0) : Disable phase 2
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- Enabled (0x1) : Enable phase 2
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- <b>Auto</b> (0x2) : Use the current default method (Default)
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**/
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UINT32 DmiGen3EqPh2Enable : 2;
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/**
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Offset 28:4 :
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<b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
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- <b>Auto</b> (0x0) : Use the current default method (Default)
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- HwEq (0x1) : Use Adaptive Hardware Equalization
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- SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
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- Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
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- Disabled (0x4) : Bypass Equalization Phase 3
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**/
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UINT32 DmiGen3EqPh3Method : 3;
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/**
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Offset 28:7 :
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<b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
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- Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
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- <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
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**/
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UINT32 DmiGen3ProgramStaticEq : 1;
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UINT32 RsvdBits0 : 24; ///< Offset 28:8 :Reserved for future use
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/**
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Offset 32:0 :
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Select when PCIe ASPM programming will happen in relation to the Oprom
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- <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom. (Default)
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- After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.
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**/
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UINT32 InitPcieAspmAfterOprom : 1;
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UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserved for future use
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UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
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UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
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UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
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/**
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Offset 48/60 :
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DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
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has to be specified based upon platform design and must follow the guideline. Default is 12.
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**/
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UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
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UINT8 DmiDeEmphasis; ///< Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
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UINT8 Rsvd0[3]; ///< Offset 65
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} PCIE_PEI_PREMEM_CONFIG;
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/**
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CPU PCIe Root Port Pre-Memory Configuration
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Contains Root Port settings and capabilities
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<b>Revision 1</b>: - Initial version.
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<b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
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<b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
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<b>Revision 4</b>: - Adding CDR Relock Setup Variable
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Root Port enabling mask.
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Bit0 presents RP1, Bit1 presents RP2, and so on.
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0: Disable; <b>1: Enable</b>.
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**/
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UINT32 RpEnabledMask;
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/**
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Assertion on Link Down GPIOs
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- <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
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- Enabled (0x1) : Enable assertion on Link Down GPIOs
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**/
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UINT8 LinkDownGpios;
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/**
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Enable ClockReq Messaging
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- <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
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- Enabled (0x1) : Enable ClockReq Messaging
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**/
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UINT8 ClkReqMsgEnable;
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/**
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Dekel Recipe Workaround
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<b>2</b>
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1=Minimal, 9=Maximum,
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**/
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UINT8 DekelSquelchWa; // Deprecated variable
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UINT8 Rsvd0[1];
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/**
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Determines each PCIE Port speed capability.
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<b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
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**/
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UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
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/**
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To Enable/Disable CDR Relock
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<b>0: Disable</b>; 1: Enable
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**/
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UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
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/**
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This policy is used while programming DEKEL Recipe
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<b>0: Disable</b>; 1: Enable
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**/
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UINT8 Xl1el[CPU_PCIE_MAX_ROOT_PORTS];
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} CPU_PCIE_RP_PREMEM_CONFIG;
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typedef enum {
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CpuPcieOverrideDisabled = 0,
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CpuPcieL1L2Override = 0x01,
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CpuPcieL1SubstatesOverride = 0x02,
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CpuPcieL1L2AndL1SubstatesOverride = 0x03,
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CpuPcieLtrOverride = 0x04
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} CPU_PCIE_OVERRIDE_CONFIG;
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/**
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PCIe device table entry entry
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The PCIe device table is being used to override PCIe device ASPM settings.
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To take effect table consisting of such entries must be instelled as PPI
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on gPchPcieDeviceTablePpiGuid.
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Last entry VendorId must be 0.
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**/
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typedef struct {
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UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
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UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
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UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
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UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
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UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
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UINT8 EndPointAspm; ///< Override device ASPM (see: CPU_PCIE_ASPM_CONTROL)
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///< Bit 1 must be set in OverrideConfig for this field to take effect
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UINT16 OverrideConfig; ///< The override config bitmap (see: CPU_PCIE_OVERRIDE_CONFIG).
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/**
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The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
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This field can be zero if only the L1 Substate value is going to be override.
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**/
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UINT16 L1SubstatesCapOffset;
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/**
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L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
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Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
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Only bit [3:0] are applicable. Other bits are ignored.
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**/
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UINT8 L1SubstatesCapMask;
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/**
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L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sCommonModeRestoreTime;
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/**
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L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sTpowerOnScale;
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/**
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L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
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L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
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If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
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and only L1SubstatesCapOffset is override.
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**/
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UINT8 L1sTpowerOnValue;
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/**
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SnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BITS[14:13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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This field takes effect only if bit 3 is set in OverrideConfig.
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**/
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UINT16 SnoopLatency;
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/**
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NonSnoopLatency bit definition
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Note: All Reserved bits must be set to 0
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BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
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When clear values in bits 9:0 will be ignored
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BITS[14:13] - Reserved
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BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
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000b - 1 ns
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001b - 32 ns
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010b - 1024 ns
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011b - 32,768 ns
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100b - 1,048,576 ns
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101b - 33,554,432 ns
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110b - Reserved
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111b - Reserved
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BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
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the scale in bits 12:10
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This field takes effect only if bit 3 is set in OverrideConfig.
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**/
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UINT16 NonSnoopLatency;
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/**
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Forces LTR override to be permanent
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The default way LTR override works is:
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rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
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This settings allows force override of LTR mechanism. If it's enabled, then:
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rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
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**/
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UINT8 ForceLtrOverride;
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UINT8 Reserved[3];
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} CPU_PCIE_DEVICE_OVERRIDE;
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enum CPU_PCIE_SPEED {
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CpuPcieAuto,
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CpuPcieGen1,
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CpuPcieGen2,
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CpuPcieGen3,
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CpuPcieGen4,
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CpuPcieGen5
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};
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///
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/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
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///
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typedef enum {
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CpuPcieAspmDisabled,
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CpuPcieAspmL0s,
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CpuPcieAspmL1,
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CpuPcieAspmL0sL1,
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CpuPcieAspmAutoConfig,
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CpuPcieAspmMax
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} CPU_PCIE_ASPM_CONTROL;
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/**
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Refer to SA EDS for the SA implementation values corresponding
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to below PCI-E spec defined ranges
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**/
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typedef enum {
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CpuPcieL1SubstatesDisabled,
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CpuPcieL1SubstatesL1_1,
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CpuPcieL1SubstatesL1_1_2,
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CpuPcieL1SubstatesMax
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} CPU_PCIE_L1SUBSTATES_CONTROL;
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enum CPU_PCIE_MAX_PAYLOAD {
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CpuPcieMaxPayload128 = 0,
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CpuPcieMaxPayload256,
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CpuPcieMaxPayload512,
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CpuPcieMaxPayloadMax
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};
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enum CPU_PCIE_COMPLETION_TIMEOUT {
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CpuPcieCompletionTO_Default,
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CpuPcieCompletionTO_50_100us,
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CpuPcieCompletionTO_1_10ms,
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CpuPcieCompletionTO_16_55ms,
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CpuPcieCompletionTO_65_210ms,
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CpuPcieCompletionTO_260_900ms,
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CpuPcieCompletionTO_1_3P5s,
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CpuPcieCompletionTO_4_13s,
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CpuPcieCompletionTO_17_64s,
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CpuPcieCompletionTO_Disabled
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};
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enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION {
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CpuPcieGen3PresetSelection,
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CpuPcieGen3CoefficientSelection
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};
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enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION {
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CpuPcieGen4PresetSelection,
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CpuPcieGen4CoefficientSelection
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};
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typedef enum {
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CpuPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as PchPcieEqHardware.
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CpuPcieEqHardware = 1, ///< Hardware equalization
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CpuPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
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} CPU_PCIE_EQ_METHOD;
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/**
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Represent lane specific PCIe Gen3 equalization parameters.
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**/
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typedef struct {
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UINT8 Cm; ///< Coefficient C-1
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UINT8 Cp; ///< Coefficient C+1
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UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
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UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
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UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
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UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
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UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
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UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
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} CPU_PCIE_EQ_LANE_PARAM;
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/**
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The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
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**/
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typedef struct {
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UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
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UINT32 VcEnabled : 1; ///< Virtual Channel. 0: Disable; <b>1: Enable</b>
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UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
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UINT32 PeerToPeer : 1; ///< Peer to Peer Mode. <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits0 : 28; ///< Reserved bits
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/**
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PCIe Gen4 Equalization Method
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- HwEq (0x1) : Hardware Equalization (Default)
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- StaticEq (0x2) : Static Equalization
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**/
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UINT8 Gen4EqPh3Method;
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UINT8 FomsCp; ///< FOM Score Board Control Policy
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UINT8 RsvdBytes0[2]; ///< Reserved bytes
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//
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// Gen3 Equalization settings
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//
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UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
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UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
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//
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// Gen4 Equalization settings
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//
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UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
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UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
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//
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// Gen5 Equalization settings
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//
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UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
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UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
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UINT32 RsvdBits1 : 8; ///< Reserved Bits
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PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
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} CPU_PCIE_ROOT_PORT_CONFIG;
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typedef struct {
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UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
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UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
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UINT8 RsvdBytes0[2]; ///<Reserved bytes
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} CPU_PCIE_ROOT_PORT_CONFIG2;
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/**
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The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
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<b>Revision 1< / b>:
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-Initial version.
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<b>Revision 2</b>:
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- SlotSelection policy added
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<b>Revision 3</b>
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- Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
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<b>Revision 4</b>:
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- Deprecating SetSecuredRegisterLock
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<b>Revision 5</b>:
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- Adding Serl
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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///
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/// These members describe the configuration of each SA PCIe root port.
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///
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CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
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///
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/// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
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/// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
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///
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CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE];
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///
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/// List of coefficients used during equalization (applicable to both software and hardware EQ)
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///
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PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; // Deprecated Policy
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PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
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UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
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///
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/// This member describes whether the PCI Express Clock Gating for each root port
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/// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
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///
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UINT32 ClockGating : 1;
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///
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/// This member describes whether the PCI Express Power Gating for each root port
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/// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
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///
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UINT32 PowerGating : 1;
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// Deprecated Policy
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/**
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<b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
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- Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
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- <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
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**/
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UINT32 PegGen3ProgramStaticEq : 1;
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// Deprecated Policy
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/**
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<b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
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- Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
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- <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
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**/
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UINT32 PegGen4ProgramStaticEq : 1;
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/**
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<b>(Test)</b> Cpu Pcie Secure Register Lock
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- Disabled (0x0)
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- <b>Enabled</b> (0x1)
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**/
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UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
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///
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/// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
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///
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UINT32 SlotSelection : 1;
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///
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/// Set/Clear Serl(Secure Equalization Register Lock)
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///
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UINT32 Serl : 1;
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UINT32 RsvdBits0 : 24;
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/**
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PCIe device override table
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The PCIe device table is being used to override PCIe device ASPM settings.
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This is a pointer points to a 32bit address. And it's only used in PostMem phase.
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Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
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Last entry VendorId must be 0.
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The prototype of this policy is:
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CPU_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
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**/
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UINT32 PcieDeviceOverrideTablePtr;
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CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
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PCIE_COMMON_CONFIG2 PcieCommonConfig2;
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} CPU_PCIE_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_PCIE_CONFIG_H_
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