/** @file
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PCH preserved MMIO resource definitions.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_PRESERVED_RESOURCES_H_
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#define _PCH_PRESERVED_RESOURCES_H_
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/**
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Detailed recommended static allocation
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+-------------------------------------------------------------------------+
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| PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF |
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+-------------------------------------------------------------------------+
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| Size | Start | End | Usage |
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| 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR |
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| 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
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| 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
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| 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
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| 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode |
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| 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused |
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| 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR |
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| 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR |
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| 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused |
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| 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
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| 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR |
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| 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused |
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| 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
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+-------------------------------------------------------------------------+
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**/
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#define PCH_PRESERVED_BASE_ADDRESS 0xFC800000 ///< Pch preserved MMIO base address
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#define PCH_PRESERVED_MMIO_SIZE 0x02000000 ///< 32MB
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#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFC800000 ///< TraceHub SW MMIO base address
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#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00800000 ///< 8MB
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#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
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#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB
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#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
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#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB
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#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address
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#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB
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#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO base address
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#define PCH_SERIAL_IO_MMIO_SIZE 0x0002C000 ///< 176KB
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#define PCH_ESPI_LGMR_BASE_ADDRESS 0xFE0B0000 ///< eSPI LGMR MMIO base address
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#define PCH_ESPI_LGMR_MMIO_SIZE 0x00010000 ///< 64KB
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#define PCH_ESPI_SEGMR_BASE_ADDRESS 0xFE0C0000 ///< Second eSPI GMR MMIO base address
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#define PCH_ESPI_SEGMR_MMIO_SIZE 0x00010000 ///< 64KB
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#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB MMIO base address
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#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB
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#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< TraceHub FW MMIO base address
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#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00200000 ///< 2MB
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#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp address for misc usage,
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#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB
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#endif // _PCH_PRESERVED_RESOURCES_H_
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