/** @file
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CPU Test Config Block.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_TEST_CONFIG_H_
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#define _CPU_TEST_CONFIG_H_
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#define CPU_TEST_CONFIG_REVISION 2
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extern EFI_GUID gCpuTestConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Test Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Removed Voltage Optimization feature.
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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UINT32 MlcStreamerPrefetcher : 1; ///< Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
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UINT32 MlcSpatialPrefetcher : 1; ///< Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>.
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UINT32 MonitorMwaitEnable : 1; ///< Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
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UINT32 MachineCheckEnable : 1; ///< Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
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UINT32 ProcessorTraceOutputScheme : 1; ///< Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
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UINT32 ProcessorTraceEnable : 1; ///< Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
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UINT32 ThreeStrikeCounterDisable : 1; ///< Disable Three strike counter; <b>0: FALSE</b>; 1: TRUE.
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UINT32 RsvdBits : 25; ///< Reserved for future use
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/**
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Base address of memory region allocated for Processor Trace.
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Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.
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- <b>NULL: Disable</b>
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**/
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EFI_PHYSICAL_ADDRESS ProcessorTraceMemBase;
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/**
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Length in bytes of memory region allocated for Processor Trace.
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Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.
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- <b>0: Disable</b>
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**/
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UINT32 ProcessorTraceMemLength;
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UINT8 Reserved0[4];
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} CPU_TEST_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_TEST_CONFIG_H_
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