/** @file
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CPU Power Management Basic Config Block.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_
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#define _CPU_POWER_MGMT_BASIC_CONFIG_H_
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#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 5
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extern EFI_GUID gCpuPowerMgmtBasicConfigGuid;
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#pragma pack (push,1)
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/**
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CPU Power Management Basic Configuration Structure.
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<b>Revision 1</b>:
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- Initial version.
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<b>Revision 2</b>:
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- Changed EnableItbm default to be disable
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- Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS driver
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<b>Revision 3</b>:
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- Add ApplyConfigTdp for TDP initialization settings based on non-cTDP or cTDP
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<b>Revision 4</b>:
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- Add Hwp Lock support
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<b>Revision 5</b>:
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- Add VccInDemotionOverride and VccInDemotionMs
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**/
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typedef struct {
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CONFIG_BLOCK_HEADER Header; ///< Config Block Header
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/**
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Sets the boot frequency starting from reset vector.
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- 0: Maximum battery performance.
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- 1: Maximum non-turbo performance.
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- <b>2: Turbo performance.</b>
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@note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
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**/
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UINT32 BootFrequency : 2; //@deprecated
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UINT32 SkipSetBootPState : 1; ///< Choose whether to skip SetBootPState function for all APs; <b>0: Do not skip</b>; 1: Skip.
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/**
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Enable or Disable Intel Speed Shift Technology.
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Enabling allows for processor control of P-state transitions.
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0: Disable; <b>1: Enable;</b> Bit 1 is ignored.
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@note Currently this feature is recommended to be enabled only on win10
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**/
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UINT32 Hwp : 2;
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/**
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Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
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HDC enables the processor to autonomously force components to enter into an idle state to lower effective frequency.
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This allows for increased package level C6 residency.
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@note Currently this feature is recommended to be enabled only on win10
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**/
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UINT32 HdcControl : 2;
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UINT32 PowerLimit2 : 1; ///< Enable or Disable short duration Power Limit (PL2). 0: Disable; <b>1: Enable</b>
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UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; <b>0: Disable</b>; 1: Enable (Lock).
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UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. <b>Default: 0</b>.
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UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615h lock; <b>0: Disable</b>; 1: Enable (Lock).
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UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601h lock; <b>0: Disable</b>; 1: Enable (Lock).
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/**
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Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.
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For Y SKU, the recommended default for this policy is <b>1: Enabled</b>, which indicates throttling below P1 is allowed.
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For all other SKUs the recommended default are <b>0: Disabled</b>.
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**/
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UINT32 TccOffsetClamp : 1;
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UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: Disabled; <b>1: Enabled (Lock)</b>.
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UINT32 TurboMode : 1; ///< Enable or Disable Turbo Mode. Disable; <b>1: Enable</b>
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UINT32 HwpInterruptControl : 1; ///< Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; <b>0: Disable</b>; 1: Enable.
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UINT32 ApplyConfigTdp : 1; ///< Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; <b>1: cTDP</b>.
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UINT32 HwpLock : 1; ///< HWP Lock in MISC PWR MGMT MSR 1AAh; <b>0: Disable</b>; 1: Enable (Lock).
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UINT32 VccInDemotionOverride : 1; ///< Enable VccIn Demotion Override configuration. <b>0: Disable</b>; 1: Enable.
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UINT32 RsvdBits : 6; ///< Reserved for future use.
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/**
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1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking parts: LFM to Fused 1-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
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**/
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UINT8 OneCoreRatioLimit;
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/**
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2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 TwoCoreRatioLimit;
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/**
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3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 ThreeCoreRatioLimit;
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/**
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4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 FourCoreRatioLimit;
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/**
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5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 FiveCoreRatioLimit;
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/**
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6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 SixCoreRatioLimit;
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/**
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7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 SevenCoreRatioLimit;
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/**
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8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.
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Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
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- This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
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**/
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UINT8 EightCoreRatioLimit;
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/**
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TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated.
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TCC will be activated at (TCC Activation Temperature - TCC Activation Offset), in degrees Celcius.
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For Y SKU, the recommended default for this policy is <b>10</b>
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For all other SKUs the recommended default are <b>0</b>, causing TCC to activate at TCC Activation temperature.
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@note The policy is recommended for validation purpose only.
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**/
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UINT8 TccActivationOffset;
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/**
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Intel Turbo Boost Max Technology 3.0
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Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores.
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<b>0: Disable</b>; 1: Enable;
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**/
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UINT8 EnableItbm : 1;
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/**
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@deprecated: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver
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Enabling it will load the driver upon ACPI device with HID = INT3510.
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<b> 0: Disable;</b> 1: Enable;
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**/
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UINT8 EnableItbmDriver : 1;
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/**
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Per Core P State OS control mode
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Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1. When set, the highest core request is used for all other core requests.
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0: Disable;<b> 1: Enable;</b>
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**/
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UINT8 EnablePerCorePState : 1;
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/**
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HwP Autonomous Per Core P State
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Disabling will set Bit 30 = 1, command 0x11. When set, autonomous will request the same value
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for all cores all the time.
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0: Disable;<b> 1: Enable;</b>
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**/
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UINT8 EnableHwpAutoPerCorePstate : 1;
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/**
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HwP Autonomous EPP grouping.
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Disabling will set Bit 29 = 1, command 0x11. When set, autonomous will not necesarrily request the same value
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for all cores with same EPP.
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Enabling will clean Bit 29 = 0, command 0x11. Autonomous will request same values for all cores with same EPP.
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0: Disable;<b> 1: Enable;</b>
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**/
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UINT8 EnableHwpAutoEppGrouping : 1;
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/**
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EPB override over PECI
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Enable by sending pcode command 0x2b , subcommand 0x3 to 1.
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This will allow OOB EPB PECI override control.
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<b>0: Disable;</b> 1: Enable;
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**/
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UINT8 EnableEpbPeciOverride : 1;
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/**
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Support for Fast MSR for IA32_HWP_REQUEST.
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On systems with HwP enabled, if this feature is available as indicated by MSR 0x65F[0] = 1,
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set MSR 0x657[0] = 1.
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0: Disable; <b> 1: Enable;</b>
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**/
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UINT8 EnableFastMsrHwpReq : 1;
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UINT8 ReservedBits1 : 1; ///< Reserved for future use.
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UINT8 MinRingRatioLimit; ///< Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
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UINT8 MaxRingRatioLimit; ///< Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
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/**
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Package Long duration turbo mode power limit (PL1).
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Default is the TDP power limit of processor. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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**/
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UINT16 PowerLimit1;
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/**
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Package Short duration turbo mode power limit (PL2). Allows for short excursions above TDP power limit.
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Default = 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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**/
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UINT16 PowerLimit2Power;
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/**
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Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit.
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<b>Default: 0</b>. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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**/
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UINT16 PowerLimit3;
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/**
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Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limit, it will never be exceeded.
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Power is premptively lowered before limit is reached. <b>Default: 0</b>. Range 0-65535.
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Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
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**/
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UINT16 PowerLimit4;
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/**
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Package Long duration turbo mode power limit (PL1) time window in seconds.
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Used in calculating the average power over time.
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Mobile: <b> 28s</b>
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Desktop: <b> 8s</b>
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Range: 0 - 128s
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**/
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UINT32 PowerLimit1Time;
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UINT32 PowerLimit3Time; ///< Package PL3 time window. Range from 3ms to 64ms.
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/**
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Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).
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For Y SKU, the recommended default for this policy is <b>5000: 5 seconds</b>, For all other SKUs the recommended default are <b>0: Disabled</b>
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**/
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UINT32 TccOffsetTimeWindowForRatl;
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/**
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Customize the VccIn Demotion in ms accordingly. Values used by OEM expected to be in lower end of 1-30 ms range.
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Value 1 means 1ms, value 2 means 2ms, and so on. Value 0 will disable VccIn Demotion knob.
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<b> It's 30ms by silicon default</b>.
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**/
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UINT32 VccInDemotionMs;
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} CPU_POWER_MGMT_BASIC_CONFIG;
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#pragma pack (pop)
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#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_
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