/** @file
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Functions and types shared by the SMM accessor PEI and DXE modules.
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Copyright (C) 2015, Red Hat, Inc.
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Copyright (C) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Guid/AcpiS3Context.h>
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#include <Register/X58Ich10.h>
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#include <Library/DebugLib.h>
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#include <Library/PciLib.h>
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#include "SmramInternal.h"
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BOOLEAN gLockState;
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BOOLEAN gOpenState;
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/**
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Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and
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OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object,
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from the D_LCK and T_EN bits.
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PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rely on
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the LockState and OpenState fields being up-to-date on entry, and they need
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to restore the same invariant on exit, if they touch the bits in question.
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@param[out] LockState Reflects the D_LCK bit on output; TRUE iff SMRAM is
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locked.
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@param[out] OpenState Reflects the inverse of the T_EN bit on output; TRUE
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iff SMRAM is open.
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**/
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VOID
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GetStates (
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OUT BOOLEAN *LockState,
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OUT BOOLEAN *OpenState
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)
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{
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UINT8 EsmramcVal;
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EsmramcVal = PciRead8(DRAMC_REGISTER_X58(MCH_TSEGMB));
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*OpenState = !(EsmramcVal & MCH_ESMRAMC_T_EN);
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*LockState = !*OpenState;
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*OpenState = gOpenState;
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*LockState = gLockState;
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}
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//
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// The functions below follow the PEI_SMM_ACCESS_PPI and
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// EFI_SMM_ACCESS2_PROTOCOL member declarations. The PeiServices and This
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// pointers are removed (TSEG doesn't depend on them), and so is the
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// DescriptorIndex parameter (TSEG doesn't support range-wise locking).
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//
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// The LockState and OpenState members that are common to both
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// PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL are taken and updated in
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// isolation from the rest of the (non-shared) members.
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//
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EFI_STATUS
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SmramAccessOpen (
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OUT BOOLEAN *LockState,
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OUT BOOLEAN *OpenState
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)
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{
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//
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// Open TSEG by clearing T_EN.
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//
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PciAnd8(DRAMC_REGISTER_X58(MCH_TSEGMB),
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(UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff));
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gOpenState = TRUE;
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gLockState = !gOpenState;
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GetStates (LockState, OpenState);
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if (!*OpenState) {
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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SmramAccessClose (
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OUT BOOLEAN *LockState,
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OUT BOOLEAN *OpenState
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)
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{
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//
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// Close TSEG by setting T_EN.
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//
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PciOr8(DRAMC_REGISTER_X58(MCH_TSEGMB), MCH_ESMRAMC_T_EN);
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gOpenState = FALSE;
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gLockState = !gOpenState;
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GetStates (LockState, OpenState);
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if (*OpenState) {
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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SmramAccessLock (
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OUT BOOLEAN *LockState,
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IN OUT BOOLEAN *OpenState
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)
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{
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if (*OpenState) {
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return EFI_DEVICE_ERROR;
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}
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//
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// Close & lock TSEG by setting T_EN and D_LCK.
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//
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PciOr8 (DRAMC_REGISTER_X58(MCH_TSEGMB), MCH_ESMRAMC_T_EN);
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gOpenState = FALSE;
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gLockState = !gOpenState;
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GetStates (LockState, OpenState);
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if (*OpenState || !*LockState) {
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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EFI_STATUS
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SmramAccessGetCapabilities (
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IN BOOLEAN LockState,
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IN BOOLEAN OpenState,
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IN OUT UINTN *SmramMapSize,
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IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
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)
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{
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UINTN OriginalSize;
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UINT32 TsegMemoryBaseMb, TsegMemoryBase;
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UINT64 CommonRegionState;
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UINT8 TsegSizeBits;
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OriginalSize = *SmramMapSize;
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*SmramMapSize = DescIdxCount * sizeof *SmramMap;
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if (OriginalSize < *SmramMapSize) {
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return EFI_BUFFER_TOO_SMALL;
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}
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//
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// Read the TSEG Memory Base register.
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//
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TsegMemoryBaseMb = PciRead32(DRAMC_REGISTER_X58(MCH_TSEGMB));
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TsegMemoryBaseMb = 0xDF800000;
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TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;
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//
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// Precompute the region state bits that will be set for all regions.
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//
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CommonRegionState = (OpenState ? EFI_SMRAM_OPEN : EFI_SMRAM_CLOSED) |
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(LockState ? EFI_SMRAM_LOCKED : 0) |
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EFI_CACHEABLE;
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//
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// The first region hosts an SMM_S3_RESUME_STATE object. It is located at the
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// start of TSEG. We round up the size to whole pages, and we report it as
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// EFI_ALLOCATED, so that the SMM_CORE stays away from it.
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//
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SmramMap[DescIdxSmmS3ResumeState].PhysicalStart = TsegMemoryBase;
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SmramMap[DescIdxSmmS3ResumeState].CpuStart = TsegMemoryBase;
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SmramMap[DescIdxSmmS3ResumeState].PhysicalSize =
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EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));
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SmramMap[DescIdxSmmS3ResumeState].RegionState =
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CommonRegionState | EFI_ALLOCATED;
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//
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// Get the TSEG size bits from the ESMRAMC register.
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//
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TsegSizeBits = PciRead8 (DRAMC_REGISTER_X58(MCH_TSEGMB)) &
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MCH_ESMRAMC_TSEG_MASK;
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TsegSizeBits = MCH_ESMRAMC_TSEG_8MB;
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//
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// The second region is the main one, following the first.
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//
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SmramMap[DescIdxMain].PhysicalStart =
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SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
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SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
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SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
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SmramMap[DescIdxMain].PhysicalSize =
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(TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
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TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
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SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
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SmramMap[DescIdxMain].RegionState = CommonRegionState;
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return EFI_SUCCESS;
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}
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