/** @file
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This driver is responsible for the registration of child drivers
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and the abstraction of the QNC SMI sources.
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Copyright (c) 2013-2015 Intel Corporation.
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Include common header file for this module.
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//
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#include "CommonHeader.h"
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#include "QNCSmmHelpers.h"
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//
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// Help handle porting bit shifts to IA-64.
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//
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#define BIT_ZERO 0x00000001
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VOID
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QNCSmmPublishDispatchProtocols(
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VOID
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)
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{
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UINTN Index;
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EFI_STATUS Status;
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//
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// Install protocol interfaces.
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//
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for (Index = 0; Index < NUM_PROTOCOLS; Index++) {
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Status = gSmst->SmmInstallProtocolInterface (
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&mPrivateData.InstallMultProtHandle,
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mPrivateData.Protocols[Index].Guid,
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EFI_NATIVE_INTERFACE,
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&mPrivateData.Protocols[Index].Protocols.Generic
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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EFI_STATUS
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QNCSmmInitHardware(
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VOID
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)
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/*++
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Routine Description:
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Initialize bits that aren't necessarily related to an SMI source.
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Dependencies:
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gSmst - SMM System Table; contains an entry for SMM CPU IO
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Returns:
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EFI_SUCCESS. Asserts, otherwise.
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--*/
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{
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EFI_STATUS Status;
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//
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// Clear all SMIs
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//
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QNCSmmClearSmi();
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Status = QNCSmmEnableGlobalSmiBit ();
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ASSERT_EFI_ERROR (Status);
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//
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// Be *really* sure to clear all SMIs
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//
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QNCSmmClearSmi ();
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return EFI_SUCCESS;
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}
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EFI_STATUS
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QNCSmmEnableGlobalSmiBit (
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VOID
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)
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/*++
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Routine Description:
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Enables the QNC to generate SMIs. Note that no SMIs will be generated
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if no SMI sources are enabled. Conversely, no enabled SMI source will
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generate SMIs if SMIs are not globally enabled. This is the main
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switchbox for SMI generation.
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Arguments:
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None
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Returns:
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EFI_SUCCESS.
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Asserts, otherwise.
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--*/
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{
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UINT32 NewValue;
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//
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// Enable SMI globally
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//
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NewValue = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
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NewValue |= SMI_EN;
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QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, NewValue);
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return EFI_SUCCESS;
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}
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EFI_STATUS
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QNCSmmClearSmi(
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VOID
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)
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/*++
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Routine Description:
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Clears the SMI after all SMI source have been processed.
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Note that this function will not work correctly (as it is
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written) unless all SMI sources have been processed.
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A revision of this function could manually clear all SMI
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status bits to guarantee success.
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Returns:
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EFI_SUCCESS.
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Asserts, otherwise.
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--*/
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{
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BOOLEAN EosSet;
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BOOLEAN SciEn;
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UINT32 Pm1Cnt = 0;
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UINT16 Pm1Sts = 0;
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UINT32 Gpe0Sts = 0;
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UINT32 SmiSts = 0;
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//
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// Determine whether an ACPI OS is present (via the SCI_EN bit)
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//
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Pm1Cnt = IoRead32(PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
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SciEn = (BOOLEAN)((Pm1Cnt & B_QNC_PM1BLK_PM1C_SCIEN) == B_QNC_PM1BLK_PM1C_SCIEN);
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if (SciEn == FALSE) {
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//
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// Clear any SMIs that double as SCIs (when SCI_EN==0)
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//
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Pm1Sts = (B_QNC_PM1BLK_PM1S_WAKE | B_QNC_PM1BLK_PM1S_PCIEWSTS | B_QNC_PM1BLK_PM1S_RTC | B_QNC_PM1BLK_PM1S_GLOB | B_QNC_PM1BLK_PM1S_TO);
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Gpe0Sts = B_QNC_GPE0BLK_GPE0S_ALL;
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IoOr16((PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1S), Pm1Sts);
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IoOr32(((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_GPE0S), Gpe0Sts);
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}
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//
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// Clear all SMIs that are unaffected by SCI_EN
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//
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SmiSts = IoRead32((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS);
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SmiSts |= B_QNC_GPE0BLK_SMIS_ALL;
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IoWrite32(((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS), SmiSts);
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//
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// Try to clear the EOS bit. ASSERT on an error
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//
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EosSet = QNCSmmSetAndCheckEos();
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ASSERT (EosSet);
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return EFI_SUCCESS;
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}
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BOOLEAN
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QNCSmmSetAndCheckEos(
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VOID
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)
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{
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//
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// Reset the QNC to generate subsequent SMIs
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//
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IoOr32(((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_SMIS), B_QNC_GPE0BLK_SMIS_EOS);
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return TRUE;
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}
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BOOLEAN
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QNCSmmGetSciEn(
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)
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{
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BOOLEAN SciEn;
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UINT32 Pm1Cnt;
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//
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// Determine whether an ACPI OS is present (via the SCI_EN bit)
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//
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Pm1Cnt = IoRead32(PcdGet16 (PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C);
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SciEn = (BOOLEAN)((Pm1Cnt & B_QNC_PM1BLK_PM1C_SCIEN) == B_QNC_PM1BLK_PM1C_SCIEN);
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return SciEn;
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}
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//
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// These may or may not need to change w/ the QNC version; they're highly IA-32 dependent, though.
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//
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BOOLEAN
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ReadBitDesc (
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CONST QNC_SMM_BIT_DESC *BitDesc
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)
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{
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UINT64 Register;
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UINT32 PciBus;
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UINT32 PciDev;
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UINT32 PciFun;
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UINT32 PciReg;
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BOOLEAN BitWasOne;
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ASSERT (BitDesc != NULL );
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ASSERT (!IS_BIT_DESC_NULL( *BitDesc ) );
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Register = 0;
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BitWasOne = FALSE;
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switch (BitDesc->Reg.Type) {
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case ACPI_ADDR_TYPE:
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//
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// Double check that we correctly read in the acpi base address
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//
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ASSERT ((PcdGet16 (PcdPm1blkIoBaseAddress) != 0x0) && ((PcdGet16 (PcdPm1blkIoBaseAddress) & 0x1) != 0x1) );
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switch (BitDesc->SizeInBytes) {
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case 0:
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//
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// Chances are that this field didn't get initialized.
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// Check your assignments to bit descriptions.
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//
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ASSERT (FALSE );
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break;
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case 1:
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Register = (UINT64) IoRead8 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi);
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break;
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case 2:
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Register = (UINT64) IoRead16 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi);
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break;
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case 4:
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Register = (UINT64) IoRead32 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi);
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break;
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default:
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//
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// Unsupported or invalid register size
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//
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ASSERT (FALSE );
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break;
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};
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if ((Register & LShiftU64 (BIT_ZERO, BitDesc->Bit)) != 0) {
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BitWasOne = TRUE;
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} else {
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BitWasOne = FALSE;
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}
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break;
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case GPE_ADDR_TYPE:
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//
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// Double check that we correctly read in the gpe base address
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//
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ASSERT (((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) != 0x0) && (((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) & 0x1) != 0x1) );
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switch (BitDesc->SizeInBytes) {
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case 0:
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//
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// Chances are that this field didn't get initialized.
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// Check your assignments to bit descriptions.
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//
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ASSERT (FALSE );
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break;
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case 1:
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Register = (UINT64) IoRead8 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe);
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break;
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case 2:
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Register = (UINT64) IoRead16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe);
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break;
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case 4:
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Register = (UINT64) IoRead32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe);
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break;
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default:
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//
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// Unsupported or invalid register size
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//
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ASSERT (FALSE );
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break;
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};
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if ((Register & LShiftU64 (BIT_ZERO, BitDesc->Bit)) != 0) {
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BitWasOne = TRUE;
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} else {
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BitWasOne = FALSE;
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}
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break;
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case MEMORY_MAPPED_IO_ADDRESS_TYPE:
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//
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// Read the register, and it with the bit to read
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//
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//
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// This code does not support reads greater then 64 bits
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//
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ASSERT (BitDesc->SizeInBytes <= 8);
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CopyMem (&Register, BitDesc->Reg.Data.Mmio, BitDesc->SizeInBytes);
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Register &= LShiftU64 (BIT0, BitDesc->Bit);
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if (Register) {
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BitWasOne = TRUE;
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} else {
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BitWasOne = FALSE;
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}
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break;
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case PCI_ADDR_TYPE:
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PciBus = BitDesc->Reg.Data.pci.Fields.Bus;
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PciDev = BitDesc->Reg.Data.pci.Fields.Dev;
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PciFun = BitDesc->Reg.Data.pci.Fields.Fnc;
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PciReg = BitDesc->Reg.Data.pci.Fields.Reg;
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switch (BitDesc->SizeInBytes) {
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case 0:
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//
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// Chances are that this field didn't get initialized.
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// Check your assignments to bit descriptions.
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ASSERT (FALSE );
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break;
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case 1:
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Register = (UINT64) PciRead8 (PCI_LIB_ADDRESS (PciBus, PciDev, PciFun, PciReg));
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break;
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case 2:
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Register = (UINT64) PciRead16 (PCI_LIB_ADDRESS (PciBus, PciDev, PciFun, PciReg));
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break;
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case 4:
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Register = (UINT64) PciRead32 (PCI_LIB_ADDRESS (PciBus, PciDev, PciFun, PciReg));
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break;
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default:
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//
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// Unsupported or invalid register size
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//
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ASSERT (FALSE );
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break;
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};
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if ((Register & LShiftU64 (BIT_ZERO, BitDesc->Bit)) != 0) {
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BitWasOne = TRUE;
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} else {
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BitWasOne = FALSE;
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}
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break;
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default:
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//
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// This address type is not yet implemented
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//
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ASSERT (FALSE );
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break;
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};
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return BitWasOne;
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}
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VOID
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WriteBitDesc (
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CONST QNC_SMM_BIT_DESC *BitDesc,
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CONST BOOLEAN ValueToWrite
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)
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{
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UINT64 Register;
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UINT64 AndVal;
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UINT64 OrVal;
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UINT32 PciBus;
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UINT32 PciDev;
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UINT32 PciFun;
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UINT32 PciReg;
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ASSERT (BitDesc != NULL);
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ASSERT (!IS_BIT_DESC_NULL(*BitDesc));
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AndVal = ~(BIT_ZERO << (BitDesc->Bit));
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OrVal = ((UINT32)ValueToWrite) << (BitDesc->Bit);
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switch (BitDesc->Reg.Type) {
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case ACPI_ADDR_TYPE:
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//
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// Double check that we correctly read in the acpi base address
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//
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ASSERT ((PcdGet16 (PcdPm1blkIoBaseAddress) != 0x0) && ((PcdGet16 (PcdPm1blkIoBaseAddress) & 0x1) != 0x1));
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switch (BitDesc->SizeInBytes) {
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case 0:
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//
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// Chances are that this field didn't get initialized.
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// Check your assignments to bit descriptions.
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//
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ASSERT (FALSE );
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break;
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case 1:
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IoAndThenOr8 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi, (UINT8)AndVal, (UINT8)OrVal);
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break;
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case 2:
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IoAndThenOr16 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi, (UINT16)AndVal, (UINT16)OrVal);
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break;
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case 4:
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IoAndThenOr32 (PcdGet16 (PcdPm1blkIoBaseAddress) + BitDesc->Reg.Data.acpi, (UINT32)AndVal, (UINT32)OrVal);
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break;
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default:
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//
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// Unsupported or invalid register size
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//
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ASSERT (FALSE );
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break;
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};
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break;
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case GPE_ADDR_TYPE:
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//
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// Double check that we correctly read in the gpe base address
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//
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ASSERT (((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) != 0x0) && (((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) & 0x1) != 0x1));
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switch (BitDesc->SizeInBytes) {
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case 0:
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//
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// Chances are that this field didn't get initialized.
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// Check your assignments to bit descriptions.
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//
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ASSERT (FALSE );
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break;
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case 1:
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IoAndThenOr8 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe, (UINT8)AndVal, (UINT8)OrVal);
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break;
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case 2:
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IoAndThenOr16 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe, (UINT16)AndVal, (UINT16)OrVal);
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break;
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case 4:
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IoAndThenOr32 ((UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + BitDesc->Reg.Data.gpe, (UINT32)AndVal, (UINT32)OrVal);
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break;
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default:
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//
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// Unsupported or invalid register size
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//
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ASSERT (FALSE );
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break;
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};
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break;
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case MEMORY_MAPPED_IO_ADDRESS_TYPE:
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//
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// Read the register, or it with the bit to set, then write it back.
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//
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//
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// This code does not support writes greater then 64 bits
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//
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ASSERT (BitDesc->SizeInBytes <= 8);
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CopyMem (&Register, BitDesc->Reg.Data.Mmio, BitDesc->SizeInBytes);
|
Register &= AndVal;
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Register |= OrVal;
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CopyMem (BitDesc->Reg.Data.Mmio, &Register, BitDesc->SizeInBytes);
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break;
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case PCI_ADDR_TYPE:
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PciBus = BitDesc->Reg.Data.pci.Fields.Bus;
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PciDev = BitDesc->Reg.Data.pci.Fields.Dev;
|
PciFun = BitDesc->Reg.Data.pci.Fields.Fnc;
|
PciReg = BitDesc->Reg.Data.pci.Fields.Reg;
|
switch (BitDesc->SizeInBytes) {
|
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case 0:
|
//
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// Chances are that this field didn't get initialized -- check your assignments
|
// to bit descriptions.
|
//
|
ASSERT (FALSE );
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break;
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case 1:
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PciAndThenOr8 (PCI_LIB_ADDRESS (PciBus, PciDev, PciFun, PciReg), (UINT8) AndVal, (UINT8) OrVal);
|
break;
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case 2:
|
PciAndThenOr16 (PCI_LIB_ADDRESS (PciBus, PciDev, PciFun, PciReg), (UINT16) AndVal, (UINT16) OrVal);
|
break;
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case 4:
|
PciAndThenOr32 (PCI_LIB_ADDRESS (PciBus, PciDev, PciFun, PciReg), (UINT32) AndVal, (UINT32) OrVal);
|
break;
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|
default:
|
//
|
// Unsupported or invalid register size
|
//
|
ASSERT (FALSE );
|
break;
|
};
|
break;
|
|
default:
|
//
|
// This address type is not yet implemented
|
//
|
ASSERT (FALSE );
|
break;
|
};
|
}
|
