/************************************************************************
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*
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* Copyright (c) 2013-2015 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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* MCU register definition
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*
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************************************************************************/
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#ifndef __IOSF_DEFINITIONS_H
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#define __IOSF_DEFINITIONS_H
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// Define each of the IOSF-SB register offsets used by MRC.
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// MCU registers (DUNIT):
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// ====
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#define DRP 0x0000
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#define DTR0 0x0001
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#define DTR1 0x0002
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#define DTR2 0x0003
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#define DTR3 0x0004
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#define DTR4 0x0005
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#define DPMC0 0x0006
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#define DPMC1 0x0007
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#define DRFC 0x0008
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#define DSCH 0x0009
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#define DCAL 0x000A
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#define DRMC 0x000B
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#define PMSTS 0x000C
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#define DCO 0x000F
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#define DSTAT 0x0020
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#define DECCCTRL 0x0060
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#define DFUSESTAT 0x0070
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#define SCRMSEED 0x0080
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#define SCRMLO 0x0081
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#define SCRMHI 0x0082
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#define MCU_CH_OFFSET 0x0040
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#define MCU_RK_OFFSET 0x0020
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////
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//
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// BEGIN DUnit register definition
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//
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t rank0Enabled :1; /**< BIT [0] Rank 0 Enable */
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uint32_t rank1Enabled :1; /**< BIT [1] Rank 1 Enable */
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uint32_t reserved0 :2;
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uint32_t dimm0DevWidth :2; /**< BIT [5:4] DIMM 0 Device Width (Rank0&1) */
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uint32_t dimm0DevDensity :2; /**< BIT [7:6] DIMM 0 Device Density */
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uint32_t reserved1 :1;
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uint32_t dimm1DevWidth :2; /**< BIT [10:9] DIMM 1 Device Width (Rank2&3) */
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uint32_t dimm1DevDensity :2; /**< BIT [12:11] DIMM 1 Device Density */
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uint32_t split64 :1; /**< BIT [13] split 64B transactions */
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uint32_t addressMap :2; /**< BIT [15:14] Address Map select */
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uint32_t reserved3 :14;
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uint32_t mode32 :1; /**< BIT [30] Select 32bit data interface*/
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uint32_t reserved4 :1;
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} field;
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} RegDRP; /**< DRAM Rank Population and Interface Register */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t dramFrequency :2; /**< DRAM Frequency (000=800,001=1033,010=1333) */
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uint32_t reserved1 :2;
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uint32_t tRP :4; /**< bit [7:4] Precharge to Activate Delay */
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uint32_t tRCD :4; /**< bit [11:8] Activate to CAS Delay */
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uint32_t tCL :3; /**< bit [14:12] CAS Latency */
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uint32_t reserved4 :1;
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uint32_t tXS :1; /**< SRX Delay */
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uint32_t reserved5 :1;
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uint32_t tXSDLL :1; /**< SRX To DLL Delay */
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uint32_t reserved6 :1;
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uint32_t tZQCS :1; /**< bit [20] ZQTS recovery Latncy */
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uint32_t reserved7 :1;
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uint32_t tZQCL :1; /**< bit [22] ZQCL recovery Latncy */
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uint32_t reserved8 :1;
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uint32_t pmeDelay :2; /**< bit [25:24] Power mode entry delay */
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uint32_t reserved9 :2;
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uint32_t CKEDLY :4; /**< bit [31:28] */
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} field;
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} RegDTR0; /**< DRAM Timing Register 0 */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t tWCL :3; /**< bit [2:0] CAS Write Latency */
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uint32_t reserved1 :1;
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uint32_t tCMD :2; /**< bit [5:4] Command transport duration */
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uint32_t reserved2 :2;
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uint32_t tWTP :4; /**< Write to Precharge */
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uint32_t tCCD :2; /**< CAS to CAS delay */
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uint32_t reserved4 :2;
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uint32_t tFAW :4; /**< Four bank Activation Window*/
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uint32_t tRAS :4; /**< Row Activation Period: */
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uint32_t tRRD :2; /**<Row activation to Row activation Delay */
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uint32_t reserved5 :2;
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uint32_t tRTP :3; /**<Read to Precharge Delay */
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uint32_t reserved6 :1;
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} field;
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} RegDTR1; /**< DRAM Timing Register 1 */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t tRRDR :3; /**< RD to RD from different ranks, same DIMM */
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uint32_t reserved1 :5;
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uint32_t tWWDR :3; /**< WR to WR from different ranks, same DIMM. */
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uint32_t reserved3 :5;
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uint32_t tRWDR :4; /**< bit [19:16] RD to WR from different ranks, same DIMM. */
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uint32_t reserved5 :12;
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} field;
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} RegDTR2; /**< DRAM Timing Register 2 */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t tWRDR :3; /**< WR to RD from different ranks, same DIMM. */
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uint32_t reserved1 :1;
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uint32_t tWRDD :3; /**< WR to RD from different DIMM. */
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uint32_t reserved2 :1;
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uint32_t tRWSR :4; /**< RD to WR Same Rank. */
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uint32_t reserved3 :1;
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uint32_t tWRSR :4; /**< WR to RD Same Rank. */
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uint32_t reserved4 :5;
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uint32_t tXP :2; /**< Time from CKE set on to any command. */
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uint32_t PWD_DLY :4; /**< Extended Power-Down Delay. */
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uint32_t EnDeRate :1;
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uint32_t DeRateOvr :1;
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uint32_t DeRateStat :1;
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uint32_t reserved5 :1;
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} field;
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} RegDTR3; /**< DRAM Timing Register 3 */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t WRODTSTRT :2; /**< WR command to ODT assert delay */
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uint32_t reserved1 :2;
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uint32_t WRODTSTOP :3; /**< Write command to ODT de-assert delay. */
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uint32_t reserved2 :1;
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uint32_t RDODTSTRT :3; /**< Read command to ODT assert delay */
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uint32_t reserved3 :1;
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uint32_t RDODTSTOP :3; /**< Read command to ODT de-assert delay */
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uint32_t ODTDIS :1; /**< ODT disable */
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uint32_t TRGSTRDIS :1; /**< Write target rank is not stretched */
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uint32_t RDODTDIS :1; /**< Disable Read ODT */
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uint32_t WRBODTDIS :1; /**< Disable Write ODT */
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uint32_t reserved5 :13;
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} field;
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} RegDTR4; /**< DRAM Timing Register 3 */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t SREntryDelay :8; /**< Self-Refresh Entry Delay: */
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uint32_t powerModeOpCode :5; /**< SPID Power Mode Opcode */
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uint32_t reserved1 :3;
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uint32_t PCLSTO :3; /**< Page Close Timeout Period */
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uint32_t reserved2 :1;
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uint32_t PCLSWKOK :1; /**< Wake Allowed For Page Close Timeout */
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uint32_t PREAPWDEN :1; /**< Send Precharge All to rank before entering Power-Down mode. */
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uint32_t reserved3 :1;
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uint32_t DYNSREN :1; /**< Dynamic Self-Refresh */
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uint32_t CLKGTDIS :1; /**< Clock Gating Disabled*/
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uint32_t DISPWRDN :1; /**< Disable Power Down*/
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uint32_t reserved4 :2;
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uint32_t REUTCLKGTDIS :1;
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uint32_t ENPHYCLKGATE :1;
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uint32_t reserved5 :2;
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} field;
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} RegDPMC0; /**< DRAM Power Management Control Register 0 */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t REFWMLO :4; /**< Refresh Opportunistic Watermark */
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uint32_t REFWMHI :4; /**< Refresh High Watermark*/
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uint32_t REFWMPNC :4; /**< Refresh Panic Watermark */
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uint32_t tREFI :3; /**< bit [14:12] Refresh Period */
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uint32_t reserved1 :1;
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uint32_t REFCNTMAX :2; /**< Refresh Max tREFI Interval */
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uint32_t reserved2 :2;
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uint32_t REFSKEWDIS :1; /**< tREFI counters */
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uint32_t REFDBTCLR :1;
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uint32_t reserved3 :2;
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uint32_t CuRefRate :3;
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uint32_t DisRefBW :1;
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uint32_t reserved4 :4;
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} field;
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} RegDRCF; /**< DRAM Refresh Control Register*/
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t reserved1 :8;
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uint32_t ZQCINT :3; /**< ZQ Calibration Short Interval: */
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uint32_t reserved2 :1;
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uint32_t SRXZQCL :2; /** < ZQ Calibration Length */
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uint32_t ZQCalType :1;
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uint32_t ZQCalStart :1;
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uint32_t TQPollStart :1;
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uint32_t TQPollRS :2;
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uint32_t reserved3 :5;
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uint32_t MRRData :8; /**< bit[31:24] */
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} field;
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} RegDCAL; /**< DRAM Calibration Control*/
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t OOOAGETRH :5; /**< Out-of-Order Aging Threshold */
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uint32_t reserved1 :3;
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uint32_t OOODIS :1; /**< Out-of-Order Disable */
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uint32_t OOOST3DIS :1; /**< Out-of-Order Disabled when RequestBD_Status is 3. */
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uint32_t reserved2 :2;
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uint32_t NEWBYPDIS :1;
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uint32_t reserved3 :3;
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uint32_t IPREQMAX :3; /** < Max In-Progress Requests stored in MC */
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uint32_t reserved4 :13;
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} field;
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} RegDSCH; /**< DRAM Scheduler Control Register */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t DRPLOCK :1; /**< DRP lock bit */
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uint32_t reserved1 :7;
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uint32_t REUTLOCK :1; /**< REUT lock bit */
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uint32_t reserved2 :19;
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uint32_t PMICTL :1; /**< PRI Control Select: 0-memory_manager, 1-hte */
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uint32_t PMIDIS :1; /**< PMIDIS Should be set is using IOSF-SB RW */
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uint32_t DIOIC :1; /**< DDRIO initialization is complete */
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uint32_t IC :1; /**< D-unit Initialization Complete */
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} field;
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} RegDCO; /**< DRAM Controller Operation Register*/
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t SBEEN :1; /**< Enable Single Bit Error Detection and Correction */
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uint32_t DBEEN :1; /**< Enable Double Bit Error Detection */
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uint32_t CBOEN :3; /**< Enable ECC Check Bits Override */
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uint32_t SYNSEL :2; /**< ECC Syndrome Bits Select for Observation */
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uint32_t CLRSBECNT :1; /**< Clear ECC Single Bit Error Count */
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uint32_t CBOV :8; /**< ECC Check Bits Override Value */
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uint32_t reserved1 :1; /**< */
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uint32_t ENCBGEN :1; /**< Enable Generation of ECC Check Bits */
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uint32_t ENCBGESWIZ :1; /**< Enable Same Chip ECC Byte Lane Swizzle */
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} field;
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} RegDECCCTRL; /**< DRAM ECC Control Register */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t FUS_DUN_ECC_DIS :1;
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uint32_t FUS_DUN_MAX_SUPPORTED_MEMORY :3;
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uint32_t FUS_DUN_MAX_DEVDEN :2;
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uint32_t RESERVED1 :1;
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uint32_t FUS_DUN_RANK2_DIS :1;
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uint32_t FUS_DUN_OOO_DIS :1;
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uint32_t FUS_DUN_MEMX8_DIS :1;
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uint32_t FUS_DUN_MEMX16_DIS :1;
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uint32_t RESERVED2 :1;
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uint32_t FUS_DUN_1N_DIS :1;
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uint32_t FUS_DUN_DQ_SCRAMBLER_DIS :1;
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uint32_t RESERVED3 :1;
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uint32_t FUS_DUN_32BIT_DRAM_IFC :1;
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} field;
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} RegDFUSESTAT;
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#pragma pack()
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//
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// END DUnit register definition
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//
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////
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////
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//
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// DRAM Initialization Structures used in JEDEC Message Bus Commands
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//
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */
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unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */
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unsigned BL :2; /**< Burst Length, CDV:1*/
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unsigned CL :1; /**< CL Reserved CDV:0 */
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unsigned RBT :1; /**< Read Burst Type */
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unsigned casLatency :3; /**< cas Latency */
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unsigned TM :1; /**< Test mode */
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unsigned dllReset :1; /**< DLL Reset */
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unsigned writeRecovery :3; /**< Write Recovery for Auto Pre-Charge: 001=2,010=3,011=4,100=5,101=6 */
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unsigned PPD :1; /**< DLL Control for Precharge Power-Down CDV:1 */
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unsigned reserved1 :3;
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unsigned rankSelect :4; /**< Rank Select */
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unsigned reserved2 :6;
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} field;
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} DramInitDDR3MRS0; /**< DDR3 Mode Register Set (MRS) Command */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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unsigned command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */
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unsigned bankAddress :3; /**< Bank Address (BA[2:0]) */
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unsigned dllEnabled :1; /**< CDV=0 */
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unsigned DIC0 :1; /**< Output Driver Impedance Control */
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unsigned rttNom0 :1; /**< RTT_nom[0] */
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unsigned MRC_AL :2; /**< Additive Latency = 0 */
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unsigned DIC1 :1; /**< Reserved */
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unsigned rttNom1 :1; /**< RTT_nom[1] */
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unsigned wlEnabled :1; /**< Write Leveling Enable */
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unsigned reserved1 :1;
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unsigned rttNom2 :1; /** < RTT_nom[2] */
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unsigned reserved2 :1;
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unsigned TDQS :1; /**< TDQS Enable */
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unsigned Qoff :1; /**< Output Buffers Disabled */
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unsigned reserved3 :3;
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unsigned rankSelect :4; /**< Rank Select */
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unsigned reserved4 :6;
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} field;
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} DramInitDDR3EMR1; /**< DDR3 Extended Mode Register 1 Set (EMRS1) Command */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */
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uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */
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uint32_t PASR :3; /**< Partial Array Self-Refresh */
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uint32_t CWL :3; /**< CAS Write Latency */
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uint32_t ASR :1; /**< Auto Self-Refresh */
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uint32_t SRT :1; /**< SR Temperature Range = 0*/
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uint32_t reserved1 :1;
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uint32_t rtt_WR :2; /**< Rtt_WR */
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uint32_t reserved2 :5;
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uint32_t rankSelect :4; /**< Rank Select */
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uint32_t reserved3 :6;
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} field;
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} DramInitDDR3EMR2; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110-ZQ,111-NOP */
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uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */
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uint32_t MPR_Location :2; /**< MPR Location */
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uint32_t MPR :1; /**< MPR: Multi Purpose Register */
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uint32_t reserved1 :13;
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uint32_t rankSelect :4; /**< Rank Select */
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uint32_t reserved2 :6;
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} field;
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} DramInitDDR3EMR3; /**< DDR3 Extended Mode Register 2 Set (EMRS2) Command */
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#pragma pack()
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#pragma pack(1)
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typedef union {
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uint32_t raw;
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struct {
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uint32_t command :3; /**< Command: 000-MRS,001-Refresh,010-Pre-charge,011-Activate,110 - ZQ Calibration,111-NOP */
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uint32_t bankAddress :3; /**< Bank Address (BA[2:0]) */
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uint32_t multAddress :16; /**< Multiplexed Address (MA[14:0]) */
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uint32_t rankSelect :2; /**< Rank Select */
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uint32_t reserved3 :8;
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} field;
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} DramInitMisc; /**< Miscellaneous DDRx Initialization Command */
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#pragma pack()
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//
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// Construct DRAM init command using DramInitXxxx pattern
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//
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#define DCMD_MRS1(rnk,dat) (0 | ((rnk)<<22) | (1<<3) | ((dat)<<6))
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#define DCMD_REF(rnk) (1 | ((rnk)<<22))
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#define DCMD_PRE(rnk) (2 | ((rnk)<<22))
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#define DCMD_PREA(rnk) (2 | ((rnk)<<22) | (BIT10<<6))
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#define DCMD_ACT(rnk,row) (3 | ((rnk)<<22) | ((row)<<6))
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#define DCMD_WR(rnk,col) (4 | ((rnk)<<22) | ((col)<<6))
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#define DCMD_RD(rnk,col) (5 | ((rnk)<<22) | ((col)<<6))
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#define DCMD_ZQCS(rnk) (6 | ((rnk)<<22))
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#define DCMD_ZQCL(rnk) (6 | ((rnk)<<22) | (BIT10<<6))
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#define DCMD_NOP(rnk) (7 | ((rnk)<<22))
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#define DDR3_EMRS1_DIC_40 (0)
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#define DDR3_EMRS1_DIC_34 (1)
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#define DDR3_EMRS2_RTTWR_60 (BIT9)
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#define DDR3_EMRS2_RTTWR_120 (BIT10)
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#define DDR3_EMRS1_RTTNOM_0 (0)
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#define DDR3_EMRS1_RTTNOM_60 (BIT2)
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#define DDR3_EMRS1_RTTNOM_120 (BIT6)
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#define DDR3_EMRS1_RTTNOM_40 (BIT6|BIT2)
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#define DDR3_EMRS1_RTTNOM_20 (BIT9)
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#define DDR3_EMRS1_RTTNOM_30 (BIT9|BIT2)
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//
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// END DRAM Init...
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//
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////
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// HOST_BRIDGE registers:
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#define HMBOUND 0x0020 //ok
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// MEMORY_MANAGER registers:
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#define BCTRL 0x0004
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#define BWFLUSH 0x0008
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#define BDEBUG1 0x00C4
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////
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//
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// BEGIN DDRIO registers
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//
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// DDR IOs & COMPs:
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#define DDRIODQ_BL_OFFSET 0x0800
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#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES/2) * DDRIODQ_BL_OFFSET)
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#define DDRIOCCC_CH_OFFSET 0x0800
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#define DDRCOMP_CH_OFFSET 0x0100
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// CH0-BL01-DQ
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#define DQOBSCKEBBCTL 0x0000
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#define DQDLLTXCTL 0x0004
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#define DQDLLRXCTL 0x0008
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#define DQMDLLCTL 0x000C
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#define B0RXIOBUFCTL 0x0010
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#define B0VREFCTL 0x0014
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#define B0RXOFFSET1 0x0018
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#define B0RXOFFSET0 0x001C
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#define B1RXIOBUFCTL 0x0020
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#define B1VREFCTL 0x0024
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#define B1RXOFFSET1 0x0028
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#define B1RXOFFSET0 0x002C
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#define DQDFTCTL 0x0030
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#define DQTRAINSTS 0x0034
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#define B1DLLPICODER0 0x0038
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#define B0DLLPICODER0 0x003C
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#define B1DLLPICODER1 0x0040
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#define B0DLLPICODER1 0x0044
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#define B1DLLPICODER2 0x0048
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#define B0DLLPICODER2 0x004C
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#define B1DLLPICODER3 0x0050
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#define B0DLLPICODER3 0x0054
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#define B1RXDQSPICODE 0x0058
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#define B0RXDQSPICODE 0x005C
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#define B1RXDQPICODER32 0x0060
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#define B1RXDQPICODER10 0x0064
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#define B0RXDQPICODER32 0x0068
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#define B0RXDQPICODER10 0x006C
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#define B01PTRCTL0 0x0070
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#define B01PTRCTL1 0x0074
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#define B01DBCTL0 0x0078
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#define B01DBCTL1 0x007C
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#define B0LATCTL0 0x0080
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#define B1LATCTL0 0x0084
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#define B01LATCTL1 0x0088
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#define B0ONDURCTL 0x008C
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#define B1ONDURCTL 0x0090
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#define B0OVRCTL 0x0094
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#define B1OVRCTL 0x0098
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#define DQCTL 0x009C
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#define B0RK2RKCHGPTRCTRL 0x00A0
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#define B1RK2RKCHGPTRCTRL 0x00A4
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#define DQRK2RKCTL 0x00A8
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#define DQRK2RKPTRCTL 0x00AC
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#define B0RK2RKLAT 0x00B0
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#define B1RK2RKLAT 0x00B4
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#define DQCLKALIGNREG0 0x00B8
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#define DQCLKALIGNREG1 0x00BC
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#define DQCLKALIGNREG2 0x00C0
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#define DQCLKALIGNSTS0 0x00C4
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#define DQCLKALIGNSTS1 0x00C8
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#define DQCLKGATE 0x00CC
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#define B0COMPSLV1 0x00D0
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#define B1COMPSLV1 0x00D4
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#define B0COMPSLV2 0x00D8
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#define B1COMPSLV2 0x00DC
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#define B0COMPSLV3 0x00E0
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#define B1COMPSLV3 0x00E4
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#define DQVISALANECR0TOP 0x00E8
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#define DQVISALANECR1TOP 0x00EC
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#define DQVISACONTROLCRTOP 0x00F0
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#define DQVISALANECR0BL 0x00F4
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#define DQVISALANECR1BL 0x00F8
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#define DQVISACONTROLCRBL 0x00FC
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#define DQTIMINGCTRL 0x010C
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// CH0-ECC
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#define ECCDLLTXCTL 0x2004
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#define ECCDLLRXCTL 0x2008
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#define ECCMDLLCTL 0x200C
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#define ECCB1DLLPICODER0 0x2038
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#define ECCB1DLLPICODER1 0x2040
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#define ECCB1DLLPICODER2 0x2048
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#define ECCB1DLLPICODER3 0x2050
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#define ECCB01DBCTL0 0x2078
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#define ECCB01DBCTL1 0x207C
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#define ECCCLKALIGNREG0 0x20B8
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#define ECCCLKALIGNREG1 0x20BC
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#define ECCCLKALIGNREG2 0x20C0
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// CH0-CMD
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#define CMDOBSCKEBBCTL 0x4800
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#define CMDDLLTXCTL 0x4808
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#define CMDDLLRXCTL 0x480C
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#define CMDMDLLCTL 0x4810
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#define CMDRCOMPODT 0x4814
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#define CMDDLLPICODER0 0x4820
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#define CMDDLLPICODER1 0x4824
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#define CMDCFGREG0 0x4840
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#define CMDPTRREG 0x4844
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#define CMDCLKALIGNREG0 0x4850
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#define CMDCLKALIGNREG1 0x4854
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#define CMDCLKALIGNREG2 0x4858
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#define CMDPMCONFIG0 0x485C
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#define CMDPMDLYREG0 0x4860
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#define CMDPMDLYREG1 0x4864
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#define CMDPMDLYREG2 0x4868
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#define CMDPMDLYREG3 0x486C
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#define CMDPMDLYREG4 0x4870
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#define CMDCLKALIGNSTS0 0x4874
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#define CMDCLKALIGNSTS1 0x4878
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#define CMDPMSTS0 0x487C
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#define CMDPMSTS1 0x4880
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#define CMDCOMPSLV 0x4884
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#define CMDBONUS0 0x488C
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#define CMDBONUS1 0x4890
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#define CMDVISALANECR0 0x4894
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#define CMDVISALANECR1 0x4898
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#define CMDVISACONTROLCR 0x489C
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#define CMDCLKGATE 0x48A0
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#define CMDTIMINGCTRL 0x48A4
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// CH0-CLK-CTL
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#define CCOBSCKEBBCTL 0x5800
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#define CCRCOMPIO 0x5804
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#define CCDLLTXCTL 0x5808
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#define CCDLLRXCTL 0x580C
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#define CCMDLLCTL 0x5810
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#define CCRCOMPODT 0x5814
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#define CCDLLPICODER0 0x5820
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#define CCDLLPICODER1 0x5824
|
#define CCDDR3RESETCTL 0x5830
|
#define CCCFGREG0 0x5838
|
#define CCCFGREG1 0x5840
|
#define CCPTRREG 0x5844
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#define CCCLKALIGNREG0 0x5850
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#define CCCLKALIGNREG1 0x5854
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#define CCCLKALIGNREG2 0x5858
|
#define CCPMCONFIG0 0x585C
|
#define CCPMDLYREG0 0x5860
|
#define CCPMDLYREG1 0x5864
|
#define CCPMDLYREG2 0x5868
|
#define CCPMDLYREG3 0x586C
|
#define CCPMDLYREG4 0x5870
|
#define CCCLKALIGNSTS0 0x5874
|
#define CCCLKALIGNSTS1 0x5878
|
#define CCPMSTS0 0x587C
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#define CCPMSTS1 0x5880
|
#define CCCOMPSLV1 0x5884
|
#define CCCOMPSLV2 0x5888
|
#define CCCOMPSLV3 0x588C
|
#define CCBONUS0 0x5894
|
#define CCBONUS1 0x5898
|
#define CCVISALANECR0 0x589C
|
#define CCVISALANECR1 0x58A0
|
#define CCVISACONTROLCR 0x58A4
|
#define CCCLKGATE 0x58A8
|
#define CCTIMINGCTL 0x58AC
|
// COMP
|
#define CMPCTRL 0x6800
|
#define SOFTRSTCNTL 0x6804
|
#define MSCNTR 0x6808
|
#define NMSCNTRL 0x680C
|
#define LATCH1CTL 0x6814
|
#define COMPVISALANECR0 0x681C
|
#define COMPVISALANECR1 0x6820
|
#define COMPVISACONTROLCR 0x6824
|
#define COMPBONUS0 0x6830
|
#define TCOCNTCTRL 0x683C
|
#define DQANAODTPUCTL 0x6840
|
#define DQANAODTPDCTL 0x6844
|
#define DQANADRVPUCTL 0x6848
|
#define DQANADRVPDCTL 0x684C
|
#define DQANADLYPUCTL 0x6850
|
#define DQANADLYPDCTL 0x6854
|
#define DQANATCOPUCTL 0x6858
|
#define DQANATCOPDCTL 0x685C
|
#define CMDANADRVPUCTL 0x6868
|
#define CMDANADRVPDCTL 0x686C
|
#define CMDANADLYPUCTL 0x6870
|
#define CMDANADLYPDCTL 0x6874
|
#define CLKANAODTPUCTL 0x6880
|
#define CLKANAODTPDCTL 0x6884
|
#define CLKANADRVPUCTL 0x6888
|
#define CLKANADRVPDCTL 0x688C
|
#define CLKANADLYPUCTL 0x6890
|
#define CLKANADLYPDCTL 0x6894
|
#define CLKANATCOPUCTL 0x6898
|
#define CLKANATCOPDCTL 0x689C
|
#define DQSANAODTPUCTL 0x68A0
|
#define DQSANAODTPDCTL 0x68A4
|
#define DQSANADRVPUCTL 0x68A8
|
#define DQSANADRVPDCTL 0x68AC
|
#define DQSANADLYPUCTL 0x68B0
|
#define DQSANADLYPDCTL 0x68B4
|
#define DQSANATCOPUCTL 0x68B8
|
#define DQSANATCOPDCTL 0x68BC
|
#define CTLANADRVPUCTL 0x68C8
|
#define CTLANADRVPDCTL 0x68CC
|
#define CTLANADLYPUCTL 0x68D0
|
#define CTLANADLYPDCTL 0x68D4
|
#define CHNLBUFSTATIC 0x68F0
|
#define COMPOBSCNTRL 0x68F4
|
#define COMPBUFFDBG0 0x68F8
|
#define COMPBUFFDBG1 0x68FC
|
#define CFGMISCCH0 0x6900
|
#define COMPEN0CH0 0x6904
|
#define COMPEN1CH0 0x6908
|
#define COMPEN2CH0 0x690C
|
#define STATLEGEN0CH0 0x6910
|
#define STATLEGEN1CH0 0x6914
|
#define DQVREFCH0 0x6918
|
#define CMDVREFCH0 0x691C
|
#define CLKVREFCH0 0x6920
|
#define DQSVREFCH0 0x6924
|
#define CTLVREFCH0 0x6928
|
#define TCOVREFCH0 0x692C
|
#define DLYSELCH0 0x6930
|
#define TCODRAMBUFODTCH0 0x6934
|
#define CCBUFODTCH0 0x6938
|
#define RXOFFSETCH0 0x693C
|
#define DQODTPUCTLCH0 0x6940
|
#define DQODTPDCTLCH0 0x6944
|
#define DQDRVPUCTLCH0 0x6948
|
#define DQDRVPDCTLCH0 0x694C
|
#define DQDLYPUCTLCH0 0x6950
|
#define DQDLYPDCTLCH0 0x6954
|
#define DQTCOPUCTLCH0 0x6958
|
#define DQTCOPDCTLCH0 0x695C
|
#define CMDDRVPUCTLCH0 0x6968
|
#define CMDDRVPDCTLCH0 0x696C
|
#define CMDDLYPUCTLCH0 0x6970
|
#define CMDDLYPDCTLCH0 0x6974
|
#define CLKODTPUCTLCH0 0x6980
|
#define CLKODTPDCTLCH0 0x6984
|
#define CLKDRVPUCTLCH0 0x6988
|
#define CLKDRVPDCTLCH0 0x698C
|
#define CLKDLYPUCTLCH0 0x6990
|
#define CLKDLYPDCTLCH0 0x6994
|
#define CLKTCOPUCTLCH0 0x6998
|
#define CLKTCOPDCTLCH0 0x699C
|
#define DQSODTPUCTLCH0 0x69A0
|
#define DQSODTPDCTLCH0 0x69A4
|
#define DQSDRVPUCTLCH0 0x69A8
|
#define DQSDRVPDCTLCH0 0x69AC
|
#define DQSDLYPUCTLCH0 0x69B0
|
#define DQSDLYPDCTLCH0 0x69B4
|
#define DQSTCOPUCTLCH0 0x69B8
|
#define DQSTCOPDCTLCH0 0x69BC
|
#define CTLDRVPUCTLCH0 0x69C8
|
#define CTLDRVPDCTLCH0 0x69CC
|
#define CTLDLYPUCTLCH0 0x69D0
|
#define CTLDLYPDCTLCH0 0x69D4
|
#define FNLUPDTCTLCH0 0x69F0
|
// PLL
|
#define MPLLCTRL0 0x7800
|
#define MPLLCTRL1 0x7808
|
#define MPLLCSR0 0x7810
|
#define MPLLCSR1 0x7814
|
#define MPLLCSR2 0x7820
|
#define MPLLDFT 0x7828
|
#define MPLLMON0CTL 0x7830
|
#define MPLLMON1CTL 0x7838
|
#define MPLLMON2CTL 0x783C
|
#define SFRTRIM 0x7850
|
#define MPLLDFTOUT0 0x7858
|
#define MPLLDFTOUT1 0x785C
|
#define MASTERRSTN 0x7880
|
#define PLLLOCKDEL 0x7884
|
#define SFRDEL 0x7888
|
#define CRUVISALANECR0 0x78F0
|
#define CRUVISALANECR1 0x78F4
|
#define CRUVISACONTROLCR 0x78F8
|
#define IOSFVISALANECR0 0x78FC
|
#define IOSFVISALANECR1 0x7900
|
#define IOSFVISACONTROLCR 0x7904
|
|
//
|
// END DDRIO registers
|
//
|
////
|
|
|
#endif
|
