/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyLibrary.h"
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/*
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Apply RVP3 PCH specific default settings
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@param[in] PchPolicyPpi The pointer to PCH Policy PPI instance
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*/
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VOID
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EFIAPI
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PchRvp3DefaultPolicy (
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IN PCH_POLICY_PPI *PchPolicy
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)
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{
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UINTN Index;
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//
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// PCIE RP
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//
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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PchPolicy->PcieConfig.RootPort[Index].ClkReqDetect = TRUE;
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PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = TRUE;
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}
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PchPolicy->PcieConfig.RootPort[0].ClkReqSupported = TRUE;
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PchPolicy->PcieConfig.RootPort[0].ClkReqNumber = 2;
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PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtle = 6;
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PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtle = 6;
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PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtle = 6;
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PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtle = 6;
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PchPolicy->PcieConfig.RootPort[4].ClkReqSupported = TRUE;
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PchPolicy->PcieConfig.RootPort[4].ClkReqNumber = 3;
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PchPolicy->PcieConfig.RootPort[5].ClkReqSupported = TRUE;
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PchPolicy->PcieConfig.RootPort[5].ClkReqNumber = 1;
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PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtle = 8;
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PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtle = 8;
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PchPolicy->PcieConfig.RootPort[8].ClkReqSupported = TRUE;
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PchPolicy->PcieConfig.RootPort[8].ClkReqNumber = 5;
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PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtle = 8;
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PchPolicy->PcieConfig.RootPort[9].ClkReqSupported = TRUE;
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PchPolicy->PcieConfig.RootPort[9].ClkReqNumber = 4;
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PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtle = 8;
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PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtle = 8;
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PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtleEnable = TRUE;
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PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtle = 8;
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//
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// SATA
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//
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PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMagEnable = TRUE;
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PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMag = 4;
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PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmpEnable = TRUE;
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PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmp = 0x2C;
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PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmpEnable = 0;
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PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmp = 0;
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//
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// USB
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//
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PchPolicy->UsbConfig.PortUsb20[0].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[0].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[0].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[0].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[1].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[1].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[1].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[1].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[2].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[2].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[2].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[2].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[3].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[3].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[3].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[3].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[4].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[4].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[4].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[4].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[5].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[5].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[5].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[5].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[6].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[6].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[6].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[6].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[7].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[7].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[7].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[7].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[8].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[8].Afe.Txiset = 5;
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PchPolicy->UsbConfig.PortUsb20[8].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[8].Afe.Pehalfbit = 1;
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PchPolicy->UsbConfig.PortUsb20[9].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[9].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[9].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[9].Afe.Pehalfbit = 1;
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// OC Map for USB2 Ports
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PchPolicy->UsbConfig.PortUsb20[ 0].OverCurrentPin = PchUsbOverCurrentPin0;
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PchPolicy->UsbConfig.PortUsb20[ 1].OverCurrentPin = PchUsbOverCurrentPin2;
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PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2;
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PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin1;
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PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPinSkip;
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// OC Map for USB3 Ports
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PchPolicy->UsbConfig.PortUsb30[0].OverCurrentPin = PchUsbOverCurrentPin0;
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PchPolicy->UsbConfig.PortUsb30[1].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1;
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PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPinSkip;
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PchPolicy->UsbConfig.SsicConfig.SsicPort[0].Enable = TRUE;
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PchPolicy->UsbConfig.SsicConfig.SsicPort[1].Enable = TRUE;
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//
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// IOAPIC
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//
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PchPolicy->IoApicConfig.BdfValid = 1;
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PchPolicy->IoApicConfig.BusNumber = 0xF0;
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PchPolicy->IoApicConfig.DeviceNumber = 0x1F;
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PchPolicy->IoApicConfig.FunctionNumber = 0;
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//
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// LAN
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//
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PchPolicy->LanConfig.K1OffEnable = TRUE;
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PchPolicy->LanConfig.ClkReqSupported = TRUE;
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PchPolicy->LanConfig.ClkReqNumber = 3;
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//
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// LOCK DOWN
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//
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PchPolicy->LockDownConfig.SpiEiss = TRUE;
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PchPolicy->LockDownConfig.BiosLock = TRUE;
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//
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// THERMAL
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//
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PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = FALSE;
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//
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// PM CONFIG
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//
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PchPolicy->PmConfig.PciClockRun = TRUE;
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//
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// DMI
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//
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PchPolicy->DmiConfig.PwrOptEnable = TRUE;
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//
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// TRACEHUB
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//
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PchPolicy->PchTraceHubConfig.MemReg0Size = 0x100000; // 1MB
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PchPolicy->PchTraceHubConfig.MemReg1Size = 0x100000; // 1MB
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}
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