/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyLibrary.h"
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#include <Library/PchPmcLib.h>
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/**
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mDevIntConfig[] table contains data on INTx and IRQ for each device.
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IRQ value for devices which use ITSS INTx->PIRQx mapping need to be set in a way
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that for each multifunctional Dxx:Fy same interrupt pins must map to the same IRQ.
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Those IRQ values will be used to update ITSS.PIRx register.
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In APIC relationship between PIRQs and IRQs is:
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PIRQA -> IRQ16
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PIRQB -> IRQ17
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PIRQC -> IRQ18
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PIRQD -> IRQ19
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PIRQE -> IRQ20
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PIRQF -> IRQ21
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PIRQG -> IRQ22
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PIRQH -> IRQ23
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Devices which use INTx->PIRQy mapping are: cAVS(in PCI mode), SMBus, GbE, TraceHub, PCIe,
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SATA, HECI, IDE-R, KT Redirection, xHCI, Thermal Subsystem, Camera IO Host Controller
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PCI Express Root Ports mapping should be programmed only with values as in below table (D27/28/29)
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otherwise _PRT methods in ACPI for RootPorts would require additional patching as
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PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Mapping
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Configured IRQ values are not used if an OS chooses to be in PIC instead of APIC mode
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = {
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// {31, 0, PchNoInt, 0}, // LPC/eSPI Interface, doesn't use interrupts
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// {31, 1, PchNoInt, 0}, // P2SB, doesn't use interrupts
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// {31, 2, PchNoInt, 0}, // PMC , doesn't use interrupts
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{31, 3, PchIntA, 16}, // cAVS(Audio, Voice, Speach), INTA is default, programmed in PciCfgSpace 3Dh
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{31, 4, PchIntA, 16}, // SMBus Controller, no default value, programmed in PciCfgSpace 3Dh
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// {31, 5, PchNoInt, 0}, // SPI , doesn't use interrupts
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{31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh
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{31, 7, PchIntA, 16}, // TraceHub, INTA is default, RO register
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{29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh
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{29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh
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{29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh
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{29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh
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{29, 4, PchIntA, 16}, // PCI Express Port 13 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{29, 5, PchIntB, 17}, // PCI Express Port 14 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{29, 6, PchIntC, 18}, // PCI Express Port 15 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{29, 7, PchIntD, 19}, // PCI Express Port 16 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{28, 0, PchIntA, 16}, // PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh
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{28, 1, PchIntB, 17}, // PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh
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{28, 2, PchIntC, 18}, // PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh
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{28, 3, PchIntD, 19}, // PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh
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{28, 4, PchIntA, 16}, // PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh
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{28, 5, PchIntB, 17}, // PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh
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{28, 6, PchIntC, 18}, // PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh
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{28, 7, PchIntD, 19}, // PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh
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{27, 0, PchIntA, 16}, // PCI Express Port 17 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 1, PchIntB, 17}, // PCI Express Port 18 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 2, PchIntC, 18}, // PCI Express Port 19 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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{27, 3, PchIntD, 19}, // PCI Express Port 20 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh
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// {24, 0, 0, 0}, // Reserved (used by RST PCIe Storage Cycle Router)
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{23, 0, PchIntA, 16}, // SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh
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{22, 0, PchIntA, 16}, // CSME: HECI #1
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{22, 1, PchIntB, 17}, // CSME: HECI #2
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{22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R)
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{22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection
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{22, 4, PchIntA, 16}, // CSME: HECI #3
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// {22, 7, PchNoInt, 0}, // CSME: WLAN
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{20, 0, PchIntA, 16}, // USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh
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{20, 2, PchIntC, 18}, // Thermal Subsystem
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// {20, 4, 0, 0}, // TraceHub Phantom (ACPI) Function
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// {18, 0, PchNoInt, 0}, // CSME: KVMcc, doesn't use interrupts
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// {18, 1, PchNoInt, 0}, // CSME: Clink, doesn't use interrupts
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// {18, 2, PchNoInt, 0}, // CSME: PMT, doesn't use interrupts
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// {18, 3, 0, 0}, // CSME: CSE UMA
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// {18, 4, 0, 0} // CSME: fTPM DMA
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{17, 5, PchIntA, 16} // SSATA controller.
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#ifdef IE_SUPPORT
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,
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// {16, 0, PchIntA, 16}, // IE: HECI #1
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// {16, 1, PchIntB, 17}, // IE: HECI #2
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// {16, 2, PchIntC, 18}, // IE: IDE-Redirection (IDE-R)
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{16, 3, PchIntD, 19} // IE: Keyboard and Text (KT) Redirection
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// {16, 4, PchIntA, 16} // IE: HECI #3
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#endif // IE_SUPPORT
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};
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//
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// mLpOnlyDevIntConfig[] table contains data on INTx and IRQ for devices that exist on SPT-LP but not on SPT-H.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mLpOnlyDevIntConfig[] = {
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{25, 1, PchIntB, 33}, // SerialIo I2C Controller #5, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[6]
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{25, 2, PchIntC, 34} // SerialIo I2C Controller #4, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[5]
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};
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/**
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mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped to IRQy).
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This information is used by systems which choose to use legacy PIC
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interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this table
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will be programmed into ITSS.PxRC registers.
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**/
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] = {
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11, // PARC: PIRQA -> IRQ11
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10, // PBRC: PIRQB -> IRQ10
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11, // PCRC: PIRQC -> IRQ11
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11, // PDRC: PIRQD -> IRQ11
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11, // PERC: PIRQE -> IRQ11
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11, // PFRC: PIRQF -> IRQ11
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11, // PGRC: PIRQG -> IRQ11
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11 // PHRC: PIRQH -> IRQ11
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};
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusRsvdAddresses[] = {
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0xA0,
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0xA2,
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0xA4,
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0xA6
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};
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/**
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PchCreatePolicyDefaults creates the default setting of PCH Policy.
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It allocates and zero out buffer, and fills in the Intel default settings.
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@param[out] PchPolicyPpi The pointer to get PCH Policy PPI instance
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@retval EFI_SUCCESS The policy default is initialized.
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@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
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**/
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EFI_STATUS
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EFIAPI
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PchCreatePolicyDefaults (
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OUT PCH_POLICY_PPI **PchPolicyPpi
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)
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{
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PCH_POLICY_PPI *PchPolicy;
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PCH_SERIES PchSeries;
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UINT32 PortIndex;
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UINT32 Index;
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UINT8 IntConfigTableEntries;
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PchSeries = GetPchSeries ();
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PchPolicy = (PCH_POLICY_PPI *) AllocateZeroPool (sizeof (PCH_POLICY_PPI));
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if (PchPolicy == NULL) {
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ASSERT (FALSE);
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Policy not listed here are set to 0/FALSE as default.
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//
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/********************************
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General initialization
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********************************/
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PchPolicy->Revision = PCH_POLICY_REVISION;
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PchPolicy->AcpiBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress);
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PchPolicy->TempMemBaseAddr = PCH_TEMP_BASE_ADDRESS;
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/********************************
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PCH general configuration
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********************************/
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//
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// Default Svid Sdid configuration
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//
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PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID;
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PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID;
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/********************************
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PCI Express related settings
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********************************/
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PchPolicy->TempPciBusMin = 2;
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PchPolicy->TempPciBusMax = 10;
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PchPolicy->PcieConfig.RpFunctionSwap = TRUE;
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for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) {
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PchPolicy->PcieConfig.RootPort[PortIndex].Aspm = PchPcieAspmAutoConfig;
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PchPolicy->PcieConfig.RootPort[PortIndex].Enable = TRUE;
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PchPolicy->PcieConfig.RootPort[PortIndex].PmSci = TRUE;
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PchPolicy->PcieConfig.RootPort[PortIndex].AcsEnabled = TRUE;
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PchPolicy->PcieConfig.RootPort[PortIndex].MaxPayload = PchPcieMaxPayload256;
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PchPolicy->PcieConfig.RootPort[PortIndex].PhysicalSlotNumber = (UINT8) PortIndex;
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PchPolicy->PcieConfig.RootPort[PortIndex].L1Substates = PchPcieL1SubstatesL1_1_2;
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//
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// PCIe LTR Configuration.
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//
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PchPolicy->PcieConfig.RootPort[PortIndex].LtrEnable = TRUE;
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if (PchSeries == PchLp) {
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PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = 0x1003;
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PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x1003;
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}
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if (PchSeries == PchH) {
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PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = 0x0846;
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PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x0846;
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}
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PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMode = 2;
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PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMultiplier = 2;
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PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideValue = 60;
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PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMode = 2;
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PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMultiplier = 2;
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PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideValue = 60;
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PchPolicy->PcieConfig.RootPort[PortIndex].Uptp = 5;
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PchPolicy->PcieConfig.RootPort[PortIndex].Dptp = 7;
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}
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for (Index = 0; Index < GetPchMaxPciePortNum (); ++Index) {
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PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = 6;
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PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = 6;
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}
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PchPolicy->PcieConfig2.SwEqCoeffList[0].Cm = 6;
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PchPolicy->PcieConfig2.SwEqCoeffList[0].Cp = 8;
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PchPolicy->PcieConfig2.SwEqCoeffList[1].Cm = 8;
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PchPolicy->PcieConfig2.SwEqCoeffList[1].Cp = 2;
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PchPolicy->PcieConfig2.SwEqCoeffList[2].Cm = 10;
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PchPolicy->PcieConfig2.SwEqCoeffList[2].Cp = 6;
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PchPolicy->PcieConfig2.SwEqCoeffList[3].Cm = 12;
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PchPolicy->PcieConfig2.SwEqCoeffList[3].Cp = 8;
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PchPolicy->PcieConfig2.SwEqCoeffList[4].Cm = 14;
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PchPolicy->PcieConfig2.SwEqCoeffList[4].Cp = 2;
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/********************************
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SATA related settings
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********************************/
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PchPolicy->SataConfig.Enable = TRUE;
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PchPolicy->SataConfig.SalpSupport = TRUE;
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PchPolicy->SataConfig.SataMode = PchSataModeAhci;
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for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) {
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PchPolicy->SataConfig.PortSettings[PortIndex].Enable = TRUE;
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PchPolicy->SataConfig.PortSettings[PortIndex].DmVal = 15;
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PchPolicy->SataConfig.PortSettings[PortIndex].DitoVal = 625;
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}
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PchPolicy->SataConfig.Rst.Raid0 = TRUE;
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PchPolicy->SataConfig.Rst.Raid1 = TRUE;
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PchPolicy->SataConfig.Rst.Raid10 = TRUE;
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PchPolicy->SataConfig.Rst.Raid5 = TRUE;
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PchPolicy->SataConfig.Rst.Irrt = TRUE;
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PchPolicy->SataConfig.Rst.OromUiBanner = TRUE;
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PchPolicy->SataConfig.Rst.OromUiDelay = PchSataOromDelay2sec;
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PchPolicy->SataConfig.Rst.HddUnlock = TRUE;
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PchPolicy->SataConfig.Rst.LedLocate = TRUE;
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PchPolicy->SataConfig.Rst.IrrtOnly = TRUE;
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PchPolicy->SataConfig.Rst.SmartStorage = TRUE;
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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PchPolicy->SataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = 100;
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}
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/********************************
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sSATA related settings
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********************************/
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PchPolicy->sSataConfig.Enable = TRUE;
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// PchPolicy->sSataConfig.TestMode = FALSE;
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// PchPolicy->sSataConfig.LegacyMode = FALSE;
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PchPolicy->sSataConfig.SalpSupport = TRUE;
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// PchPolicy->sSataConfig.eSATASpeedLimit = FALSE;
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PchPolicy->sSataConfig.SataMode = PchSataModeAhci;
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// PchPolicy->sSataConfig.SpeedLimit = PchsSataSpeedDefault;
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for (PortIndex = 0; PortIndex < GetPchMaxsSataPortNum (); PortIndex++) {
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PchPolicy->sSataConfig.PortSettings[PortIndex].Enable = TRUE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].HotPlug = FALSE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].InterlockSw = FALSE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].External = FALSE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].SpinUp = FALSE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].SolidStateDrive = FALSE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].DevSlp = FALSE;
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// PchPolicy->sSataConfig.PortSettings[PortIndex].EnableDitoConfig = FALSE;
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PchPolicy->sSataConfig.PortSettings[PortIndex].DmVal = 15;
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PchPolicy->sSataConfig.PortSettings[PortIndex].DitoVal = 625;
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}
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// PchPolicy->sSataConfig.Rst.RaidAlternateId = FALSE;
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PchPolicy->sSataConfig.Rst.Raid0 = TRUE;
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PchPolicy->sSataConfig.Rst.Raid1 = TRUE;
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PchPolicy->sSataConfig.Rst.Raid10 = TRUE;
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PchPolicy->sSataConfig.Rst.Raid5 = TRUE;
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PchPolicy->sSataConfig.Rst.Irrt = TRUE;
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PchPolicy->sSataConfig.Rst.OromUiBanner = TRUE;
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PchPolicy->sSataConfig.Rst.OromUiDelay = PchSataOromDelay2sec;
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PchPolicy->sSataConfig.Rst.HddUnlock = TRUE;
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PchPolicy->sSataConfig.Rst.LedLocate = TRUE;
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PchPolicy->sSataConfig.Rst.IrrtOnly = TRUE;
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PchPolicy->sSataConfig.Rst.SmartStorage = TRUE;
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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//PchPolicy->sSataConfig.RstPcieStorageRemap[Index].Enable = 0;
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//PchPolicy->sSataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = 0;
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PchPolicy->sSataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = 100;
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}
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/********************************
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USB related configuration
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********************************/
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for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) {
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PchPolicy->UsbConfig.PortUsb20[PortIndex].Enable = TRUE;
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}
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for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
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PchPolicy->UsbConfig.PortUsb30[PortIndex].Enable = TRUE;
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}
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//
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//XHCI Wake On USB Disabled
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//
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PchPolicy->UsbConfig.XhciWakeOnUsb = FALSE;
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//
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// USB Port Over Current Pins mapping, please set as per board layout.
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// Default is PchUsbOverCurrentPin0(0)
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//
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PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPin1;
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PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPin1;
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PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2;
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PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPin2;
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PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPin3;
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PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPin3;
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PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin4;
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PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPin4;
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PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPin5;
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PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPin5;
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PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPin6;
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PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPin6;
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PchPolicy->UsbConfig.PortUsb20[14].OverCurrentPin = PchUsbOverCurrentPin7;
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PchPolicy->UsbConfig.PortUsb20[15].OverCurrentPin = PchUsbOverCurrentPin7;
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PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPin1;
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PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1;
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PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPin2;
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PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPin2;
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PchPolicy->UsbConfig.PortUsb30[6].OverCurrentPin = PchUsbOverCurrentPin3;
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PchPolicy->UsbConfig.PortUsb30[7].OverCurrentPin = PchUsbOverCurrentPin3;
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PchPolicy->UsbConfig.PortUsb30[8].OverCurrentPin = PchUsbOverCurrentPin4;
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PchPolicy->UsbConfig.PortUsb30[9].OverCurrentPin = PchUsbOverCurrentPin4;
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//
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// Default values of USB2 AFE settings.
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//
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for (Index = 0; Index < PCH_H_XHCI_MAX_USB2_PORTS; Index++) {
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PchPolicy->UsbConfig.PortUsb20[Index].Afe.Petxiset = 7;
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PchPolicy->UsbConfig.PortUsb20[Index].Afe.Txiset = 0;
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PchPolicy->UsbConfig.PortUsb20[Index].Afe.Predeemp = 2;
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PchPolicy->UsbConfig.PortUsb20[Index].Afe.Pehalfbit = 1;
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}
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//
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// Enable/Disable SSIC support in the setup menu
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//
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for (PortIndex = 0; PortIndex < PCH_XHCI_MAX_SSIC_PORT_COUNT; PortIndex++) {
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PchPolicy->UsbConfig.SsicConfig.SsicPort[PortIndex].Enable = FALSE;
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}
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//
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// xDCI configuration
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//
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PchPolicy->UsbConfig.XdciConfig.Enable = FALSE;
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/********************************
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Io Apic configuration
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********************************/
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PchPolicy->IoApicConfig.IoApicId = 0x02;
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PchPolicy->IoApicConfig.IoApicEntry24_119 = FALSE;
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/********************************
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HPET Configuration
|
********************************/
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PchPolicy->HpetConfig.Enable = TRUE;
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PchPolicy->HpetConfig.Base = PCH_HPET_BASE_ADDRESS;
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/********************************
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HD-Audio configuration
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********************************/
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PchPolicy->HdAudioConfig.Enable = PCH_HDAUDIO_AUTO;
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PchPolicy->HdAudioConfig.DspEnable = TRUE;
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PchPolicy->HdAudioConfig.HdAudioLinkFrequency = PchHdaLinkFreq24MHz;
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PchPolicy->HdAudioConfig.IDispLinkFrequency = PchHdaLinkFreq96MHz;
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PchPolicy->HdAudioConfig.ResetWaitTimer = 600; // Must be at least 521us (25 frames)
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PchPolicy->HdAudioConfig.DspEndpointDmic = PchHdaDmic4chArray;
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|
/********************************
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Lan configuration
|
********************************/
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PchPolicy->LanConfig.Enable = TRUE;
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/********************************
|
SMBus configuration
|
********************************/
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PchPolicy->SmbusConfig.Enable = TRUE;
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PchPolicy->SmbusConfig.SmbusIoBase = PcdGet16 (PcdSmbusBaseAddress);
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ASSERT (sizeof (mSmbusRsvdAddresses) <= PCH_MAX_SMBUS_RESERVED_ADDRESS);
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PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = sizeof (mSmbusRsvdAddresses);
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CopyMem (
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PchPolicy->SmbusConfig.RsvdSmbusAddressTable,
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mSmbusRsvdAddresses,
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sizeof (mSmbusRsvdAddresses)
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);
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|
/********************************
|
Lockdown configuration
|
********************************/
|
PchPolicy->LockDownConfig.GlobalSmi = TRUE;
|
//
|
// PCH BIOS Spec Flash Security Recommendations,
|
// Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit
|
// will mitigate malicious software attempts to replace the system BIOS option ROM with its own code.
|
// Here we always enable this as a Policy.
|
//
|
PchPolicy->LockDownConfig.BiosInterface = TRUE;
|
PchPolicy->LockDownConfig.RtcLock = TRUE;
|
|
/********************************
|
Thermal configuration.
|
********************************/
|
PchPolicy->ThermalConfig.ThermalDeviceEnable = 0;
|
PchPolicy->ThermalConfig.TsmicLock = TRUE;
|
PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE;
|
PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = TRUE;
|
PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE;
|
PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE;
|
PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE;
|
|
/********************************
|
MiscPm Configuration
|
********************************/
|
PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE;
|
PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE;
|
PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE;
|
PchPolicy->PmConfig.PowerResetStatusClear.WolOvrWkSts = TRUE;
|
|
PchPolicy->PmConfig.WakeConfig.WolEnableOverride = TRUE;
|
PchPolicy->PmConfig.WakeConfig.LanWakeFromDeepSx = TRUE;
|
|
PchPolicy->PmConfig.PchSlpS3MinAssert = PchSlpS350ms;
|
PchPolicy->PmConfig.PchSlpS4MinAssert = PchSlpS44s;
|
PchPolicy->PmConfig.PchSlpSusMinAssert = PchSlpSus4s;
|
PchPolicy->PmConfig.PchSlpAMinAssert = PchSlpA2s;
|
|
PchPolicy->PmConfig.PmcReadDisable = TRUE;
|
PchPolicy->PmConfig.SlpLanLowDc = TRUE;
|
PchPolicy->PmConfig.PciePllSsc = 0xFF;
|
|
PchPolicy->PmConfig.SlpS0Enable = TRUE;
|
|
PchPolicy->PmConfig.GrPfetDurOnDef = PchPmGrPfetDur5us;
|
|
/********************************
|
DMI related settings
|
********************************/
|
PchPolicy->DmiConfig.DmiAspm = TRUE;
|
PchPolicy->DmiConfig.DmiStopAndScreamEnable = FALSE;
|
|
/********************************
|
Serial IRQ Configuration
|
********************************/
|
PchPolicy->SerialIrqConfig.SirqEnable = TRUE;
|
PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode;
|
PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk;
|
|
|
/********************************
|
Interrupt Configuration
|
********************************/
|
IntConfigTableEntries = sizeof (mDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG);
|
ASSERT (IntConfigTableEntries <= PCH_MAX_DEVICE_INTERRUPT_CONFIG);
|
PchPolicy->PchInterruptConfig.NumOfDevIntConfig = IntConfigTableEntries;
|
CopyMem (
|
PchPolicy->PchInterruptConfig.DevIntConfig,
|
mDevIntConfig,
|
sizeof (mDevIntConfig)
|
);
|
if (GetPchSeries () == PchLp) {
|
CopyMem (
|
&(PchPolicy->PchInterruptConfig.DevIntConfig[IntConfigTableEntries]),
|
mLpOnlyDevIntConfig,
|
sizeof (mLpOnlyDevIntConfig)
|
);
|
PchPolicy->PchInterruptConfig.NumOfDevIntConfig += (sizeof (mLpOnlyDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG));
|
}
|
|
ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <= PCH_MAX_PXRC_CONFIG);
|
CopyMem (
|
PchPolicy->PchInterruptConfig.PxRcConfig,
|
mPxRcConfig,
|
sizeof (mPxRcConfig)
|
);
|
|
PchPolicy->PchInterruptConfig.GpioIrqRoute = 14;
|
PchPolicy->PchInterruptConfig.SciIrqSelect = 9;
|
PchPolicy->PchInterruptConfig.TcoIrqSelect = 9;
|
|
|
/********************************
|
Port 61h emulation
|
********************************/
|
PchPolicy->Port61hSmmConfig.Enable = TRUE;
|
|
|
/********************************
|
DCI Configuration
|
********************************/
|
PchPolicy->DciConfig.DciAutoDetect = TRUE;
|
|
/********************************
|
LPC Configuration
|
********************************/
|
PchPolicy->LpcConfig.EnhancePort8xhDecoding = TRUE;
|
|
/********************************
|
Power Optimizer related settings
|
********************************/
|
PchPolicy->SataConfig.PwrOptEnable = TRUE;
|
PchPolicy->sSataConfig.PwrOptEnable = TRUE;
|
|
|
PchPolicy->AdrConfig.PchAdrEn = FORCE_ENABLE;
|
PchPolicy->AdrConfig.AdrGpioSel = PM_SYNC_GPIO_B;
|
PchPolicy->AdrConfig.AdrHostPartitionReset = FORCE_DISABLE;
|
PchPolicy->AdrConfig.AdrTimerEn = FORCE_ENABLE;
|
PchPolicy->AdrConfig.AdrTimerVal = V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US;
|
PchPolicy->AdrConfig.AdrMultiplierVal = V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1;
|
|
*PchPolicyPpi = PchPolicy;
|
return EFI_SUCCESS;
|
}
|
|
/**
|
PchInstallPolicyPpi installs PchPolicyPpi.
|
While installed, RC assumes the Policy is ready and finalized. So please update and override
|
any setting before calling this function.
|
|
@param[in] PchPolicyPpi The pointer to PCH Policy PPI instance
|
|
@retval EFI_SUCCESS The policy is installed.
|
@retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
|
**/
|
EFI_STATUS
|
EFIAPI
|
PchInstallPolicyPpi (
|
IN PCH_POLICY_PPI *PchPolicyPpi
|
)
|
{
|
EFI_STATUS Status;
|
EFI_PEI_PPI_DESCRIPTOR *PchPolicyPpiDesc;
|
|
PchPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
|
if (PchPolicyPpiDesc == NULL) {
|
ASSERT (FALSE);
|
return EFI_OUT_OF_RESOURCES;
|
}
|
|
PchPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
|
PchPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid;
|
PchPolicyPpiDesc->Ppi = PchPolicyPpi;
|
|
//
|
// Print whole PCH_POLICY_PPI and serial out.
|
//
|
if (PchIsDwrFlow() == FALSE) {
|
PchPrintPolicyPpi (PchPolicyPpi);
|
}
|
|
//
|
// Install PCH Policy PPI
|
//
|
Status = PeiServicesInstallPpi (PchPolicyPpiDesc);
|
ASSERT_EFI_ERROR (Status);
|
return Status;
|
}
|
