/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseLib.h>
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#include <Library/MmPciBaseLib.h>
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#include <Library/PchInfoLib.h>
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#include <PchAccess.h>
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#define PCH_DO_STRINGIFY(x) #x
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#define PCH_STRINGIFY(x) PCH_DO_STRINGIFY(x)
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//
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// This module variables are used for cache the static result.
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// @note: please pay attention to the PEI phase, the module variables on ROM
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// and can't be modified.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED UINTN mLpcBaseAddr = 0;
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_STEPPING mPchStepping = PchSteppingMax;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mIsPchSupported = 0xFF;
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_SERIES mPchSeries = PchUnknownSeries;
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_GENERATION mPchGeneration = PchUnknownGeneration;
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/**
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Return Pch stepping type
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@retval PCH_STEPPING Pch stepping type
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**/
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PCH_STEPPING
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EFIAPI
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PchStepping (
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VOID
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)
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{
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UINT8 RevId;
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UINT16 LpcDeviceId;
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UINTN LpcBaseAddress;
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if (mPchStepping != PchSteppingMax) {
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return mPchStepping;
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}
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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RevId = MmioRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET);
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LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
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if (IS_PCH_H_LPC_DEVICE_ID (LpcDeviceId)) {
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switch (RevId) {
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case V_PCH_LPC_RID_0:
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mPchStepping = PchHA0;
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return PchHA0;
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case V_PCH_LPC_RID_10:
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mPchStepping = PchHB0;
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return PchHB0;
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case V_PCH_LPC_RID_20:
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mPchStepping = PchHC0;
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return PchHC0;
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case V_PCH_LPC_RID_30:
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mPchStepping = PchHD0;
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return PchHD0;
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case V_PCH_LPC_RID_31:
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mPchStepping = PchHD1;
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return PchHD1;
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default:
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %a and above\n", PCH_STRINGIFY(PCH_H_MIN_SUPPORTED_STEPPING))) ;
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return PchSteppingMax;
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}
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}
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if (IS_PCH_LP_LPC_DEVICE_ID (LpcDeviceId)) {
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switch (RevId) {
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#ifdef SIMICS_FLAG
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case V_PCH_LPC_RID_0:
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mPchStepping = PchLpA0;
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return PchLpA0;
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#endif
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case V_PCH_LPC_RID_10:
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mPchStepping = PchLpB0;
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return PchLpB0;
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case V_PCH_LPC_RID_11:
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mPchStepping = PchLpB1;
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return PchLpB1;
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case V_PCH_LPC_RID_20:
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mPchStepping = PchLpC0;
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return PchLpC0;
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case V_PCH_LPC_RID_21:
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mPchStepping = PchLpC1;
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return PchLpC1;
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default:
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %a and above\n", PCH_STRINGIFY(PCH_LP_MIN_SUPPORTED_STEPPING))) ;
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return PchSteppingMax;
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}
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}
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#ifdef SKXD_EN
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if (IS_PCH_LBG_D_SSKU_LPC_DEVICE_ID (LpcDeviceId)) {
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switch (RevId) {
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case V_PCH_LBG_LPC_RID_3:
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return LbgB1_D;
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default:
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %s and above\n", PCH_STRINGIFY(V_PCH_LBG_LPC_RID_3)));
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return PchSteppingMax;
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}
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}
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#endif // SKXD_EN
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if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) {
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if (RevId == 0) {
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return LbgA0;
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} else {
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switch (RevId) {
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case V_PCH_LBG_LPC_RID_0:
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return LbgA0;
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case V_PCH_LBG_LPC_RID_2:
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return LbgB0;
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case V_PCH_LBG_LPC_RID_3:
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return LbgB1;
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case V_PCH_LBG_LPC_RID_4:
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return LbgB2;
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case V_PCH_LBG_LPC_RID_8:
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return LbgS0;
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case V_PCH_LBG_LPC_RID_9:
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return LbgS1;
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default:
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DEBUG ((DEBUG_ERROR, "Unsupported PCH Stepping. Supporting PCH stepping starting from %s and above\n", PCH_STRINGIFY(PCH_LBG_MIN_SUPPORTED_STEPPING)));
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ASSERT (FALSE);
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return PchSteppingMax;
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}
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}
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}
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return PchSteppingMax;
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}
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/**
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Determine if PCH is supported
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@retval TRUE PCH is supported
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@retval FALSE PCH is not supported
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**/
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BOOLEAN
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IsPchSupported (
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VOID
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)
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{
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UINT16 LpcDeviceId;
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UINT16 LpcVendorId;
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UINTN LpcBaseAddress;
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if (mIsPchSupported != 0xFF) {
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return (BOOLEAN) mIsPchSupported;
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}
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
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LpcVendorId = MmioRead16 (LpcBaseAddress + PCI_VENDOR_ID_OFFSET);
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///
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/// Verify that this is a supported chipset
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///
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if ((LpcVendorId == V_PCH_LPC_VENDOR_ID) &&
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(IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)))
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{
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mIsPchSupported = TRUE;
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return TRUE;
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} else {
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DEBUG ((DEBUG_ERROR, "PCH code doesn't support the LpcDeviceId: 0x%04x!\n", LpcDeviceId));
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mIsPchSupported = FALSE;
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return FALSE;
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}
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}
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/**
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Return Pch Series
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@retval PCH_SERIES Pch Series
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**/
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PCH_SERIES
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EFIAPI
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GetPchSeries (
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VOID
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)
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{
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UINT16 LpcDeviceId;
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UINT32 PchSeries;
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UINTN LpcBaseAddress;
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if (mPchSeries != PchUnknownSeries) {
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return mPchSeries;
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}
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
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if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) {
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PchSeries = PchH;
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} else if (IS_PCH_LP_LPC_DEVICE_ID (LpcDeviceId)) {
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PchSeries = PchLp;
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} else {
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PchSeries = PchUnknownSeries;
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DEBUG ((DEBUG_ERROR, "Unsupported PCH SKU, LpcDeviceId: 0x%04x!\n", LpcDeviceId));
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ASSERT (FALSE);
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}
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mPchSeries = PchSeries;
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return PchSeries;
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}
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/**
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Return Pch Generation
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@retval PCH_GENERATION Pch Generation
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**/
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PCH_GENERATION
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EFIAPI
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GetPchGeneration (
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VOID
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)
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{
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UINT16 LpcDeviceId;
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UINT32 PchGen;
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UINTN LpcBaseAddress;
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if (mPchGeneration != PchUnknownGeneration) {
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return mPchGeneration;
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}
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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LpcDeviceId = MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
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if (IS_PCH_LBG_LPC_DEVICE_ID (LpcDeviceId)) {
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PchGen = SklPch;
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} else {
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PchGen = PchUnknownGeneration;
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DEBUG ((DEBUG_ERROR, "Unsupported PCH SKU, LpcDeviceId: 0x%04x!\n", LpcDeviceId));
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ASSERT (FALSE);
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}
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mPchGeneration = PchGen;
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return PchGen;
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}
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/**
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Get Pch Maximum Pcie Root Port Number
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@retval Pch Maximum Pcie Root Port Number
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**/
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UINT8
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EFIAPI
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GetPchMaxPciePortNum (
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VOID
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)
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{
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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switch (PchSeries) {
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case PchLp:
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return PCH_LP_PCIE_MAX_ROOT_PORTS;
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case PchH:
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return PCH_H_PCIE_MAX_ROOT_PORTS;
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default:
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return 0;
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}
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}
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/**
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Get Pch Maximum Sata Port Number
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@retval Pch Maximum Sata Port Number
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**/
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UINT8
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EFIAPI
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GetPchMaxSataPortNum (
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VOID
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)
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{
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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switch (PchSeries) {
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case PchLp:
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return PCH_LP_AHCI_MAX_PORTS;
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case PchH:
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return PCH_H_AHCI_MAX_PORTS;
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default:
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return 0;
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}
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}
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/**
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Get Pch Usb Maximum Physical Port Number
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@retval Pch Usb Maximum Physical Port Number
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**/
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UINT8
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EFIAPI
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GetPchUsbMaxPhysicalPortNum (
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VOID
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)
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{
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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switch (PchSeries) {
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case PchLp:
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return PCH_LP_XHCI_MAX_USB2_PHYSICAL_PORTS;
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case PchH:
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return PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS;
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default:
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return 0;
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}
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}
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/**
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Get Pch Maximum Usb2 Port Number of XHCI Controller
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@retval Pch Maximum Usb2 Port Number of XHCI Controller
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**/
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UINT8
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EFIAPI
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GetPchXhciMaxUsb2PortNum (
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VOID
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)
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{
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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switch (PchSeries) {
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case PchLp:
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return PCH_LP_XHCI_MAX_USB2_PORTS;
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case PchH:
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return PCH_H_XHCI_MAX_USB2_PORTS;
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default:
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return 0;
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}
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}
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/**
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Get Pch Maximum Usb3 Port Number of XHCI Controller
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@retval Pch Maximum Usb3 Port Number of XHCI Controller
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**/
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UINT8
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EFIAPI
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GetPchXhciMaxUsb3PortNum (
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VOID
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)
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{
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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switch (PchSeries) {
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case PchLp:
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return PCH_LP_XHCI_MAX_USB3_PORTS;
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case PchH:
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return PCH_H_XHCI_MAX_USB3_PORTS;
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default:
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return 0;
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}
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}
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/**
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Determine if sSata controller is present or not
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@param[in] None
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@retval TRUE or FALSE
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**/
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BOOLEAN
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EFIAPI
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GetIsPchsSataPresent (
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VOID
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)
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{
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UINT16 sSataDeviceId;
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UINTN sSataBaseAddress;
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sSataBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_EVA,
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PCI_FUNCTION_NUMBER_PCH_SSATA
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);
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sSataDeviceId = MmioRead16 ( sSataBaseAddress + PCI_DEVICE_ID_OFFSET);
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if (sSataDeviceId != 0xffff){
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return TRUE;
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}
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return FALSE;
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}
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/**
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Get Pch Maximum sSata Controller Number
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@param[in] None
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@retval Pch Maximum sSata Controller Number
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**/
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UINT8
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EFIAPI
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GetPchMaxsSataPortNum (
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VOID
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)
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{
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return PCH_SSATA_MAX_PORTS;
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}
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/**
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Get Pch Maximum Sata Controller Number
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@param[in] None
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@retval Pch Maximum Sata Controller Number
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**/
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UINT8
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EFIAPI
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GetPchMaxsSataControllerNum (
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VOID
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)
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{
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return PCH_SSATA_MAX_CONTROLLERS;
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}
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/**
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Return Pch Lpc Device Id
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@retval UINT16 Pch DeviceId
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**/
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UINT16
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EFIAPI
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GetPchLpcDeviceId (
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VOID
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)
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{
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UINTN LpcBaseAddress;
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if (mPchSeries != PchUnknownSeries) {
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return mPchSeries;
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}
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LpcBaseAddress = mLpcBaseAddr;
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if (LpcBaseAddress == 0) {
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LpcBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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mLpcBaseAddr = LpcBaseAddress;
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}
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return MmioRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
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}
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