/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#define PCI_CARD_BASE_ADDR0 0x10
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#define PCI_CARD_BASE_ADDR1 0x14
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#define PCI_CARD_BASE_ADDR2 0x18
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#define PCI_CARD_BASE_ADDR3 0x1C
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#define PCI_CARD_BASE_ADDR4 0x20
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#define PCI_CARD_BASE_ADDR5 0x24
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//RST Pcie Storage Remapped Base Address Index Value
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Name(PRBI, 0)
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//RST Pcie Storage Remapped Base Address Data Value
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Name(PRBD, 0)
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//RST Pcie Storage Endpoint Command Data
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Name(PCMD, 0)
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//RST Pcie Storage Cycle Router
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Name(NCRN, 0)
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//
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// Variables list to store corresponding value for different NVM device
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//
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Name(NITV, 0) // Interface Type
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Name(NPMV, 0) // Power Management Capability Pointer
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Name(NPCV, 0) // PCIe Capabilities Pointer
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Name(NL1V, 0) // L1SS Capability Pointer
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Name(ND2V, 0) // Endpoint L1SS Control Data2
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Name(ND1V, 0) // Endpoint L1SS Control Data1
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Name(NLRV, 0) // LTR Capability Pointer
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Name(NLDV, 0) // Endpoint LTR Data
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Name(NEAV, 0) // Endpoint LCTL Data
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Name(NEBV, 0) // Endpoint DCTL Data
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Name(NECV, 0) // Endpoint DCTL2 Data
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Name(NRAV, 0) // RootPort DCTL2 Data
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Name(NMBV, 0) // Endpoint unique MSI-X Table BAR
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Name(NMVV, 0) // Endpoint unique MSI-X Table BAR value
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Name(NPBV, 0) // Endpoint unique MSI-X PBA BAR
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Name(NPVV, 0) // Endpoint unique MSI-X PBA BAR value
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Method(EPD0, 0, Serialized) // Put Remapped Device into D0 state
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{
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RDCA(NCRN,Add(NPMV,0x04),0xFFFFFFFC,0x0,ENDPOINT_WRITE)
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}
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Method(EPD3, 0, Serialized) // Put Remapped Device into D3 state
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{
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RDCA(NCRN,Add(NPMV,0x04),0xFFFFFFFC,0x3,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device and Hidden Root Port
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// This method is called after the endpoint is to be power ungated (D3-cold to D0 unitialized)
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//
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Method(CNRS, 0, Serialized)
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{
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//
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// Return if RST Pcie Storage Remapping is disabled
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//
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If(LEqual(NITV,0))
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{
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Return(0)
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}
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//
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// Clear all BARs in Remapped Device
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//
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RDCA(NCRN,PCI_CARD_BASE_ADDR0,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR1,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR2,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR3,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR4,0x0,0x0,ENDPOINT_WRITE)
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RDCA(NCRN,PCI_CARD_BASE_ADDR5,0x0,0x0,ENDPOINT_WRITE)
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//
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// Restore Endpoint CMD and remapped BAR
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//
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RDCA(NCRN,0x4,0xFFFFFFF8,PCMD,ENDPOINT_WRITE)
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RDCA(NCRN,PRBI,0x0,PRBD,ENDPOINT_WRITE)
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//
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// Restore of Remapped Device L1 Substate if this Capability is supported
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//
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If(LNotEqual(NL1V,0))
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{
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RDCA(NCRN,Add(NL1V,0x0C),0xFFFFFF00,ND2V,ENDPOINT_WRITE)
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RDCA(NCRN,Add(NL1V,0x08),0x0000000F,And(ND1V,0xFFFFFFF0),ENDPOINT_WRITE)
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RDCA(NCRN,Add(NL1V,0x08),0xFFFFFFFF,ND1V,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device LTR if this Capability is supported
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//
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If(LNotEqual(NLRV,0))
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{
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RDCA(NCRN,Add(NLRV,0x04),0xFFFFFFFF,NLDV,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device Link Control's "Enable Clock Power Management" field and "Common Clock Configuration" field
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//
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RDCA(NCRN,Add(NPCV,0x10),0xFFFFFEBF,And(NEAV,0xFFFC),ENDPOINT_WRITE)
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//
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// Restore of Remapped Device Device Control 2 field
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//
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RDCA(NCRN,Add(NPCV,0x28),0xFFFFFBFF,NECV,ENDPOINT_WRITE)
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//
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// Restore of Remapped Device Device Control field
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//
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RDCA(NCRN,Add(NPCV,0x8),0xFFFFFF1F,NEBV,ENDPOINT_WRITE)
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//
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// Restore of Hidden Root Port field
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//
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RDCA(NCRN,0x68,0xFFFFFBFF,NRAV,ROOTPORT_WRITE)
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//
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// Check CCC bit
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// If this bit is 1, perform link retrain by setting the "Retrain Link" bit
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//
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If(LEqual(And(NEAV,0x40),0x40))
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{
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RDCA(NCRN,0x50,0xFFFFFFDF,0x20,ROOTPORT_WRITE)
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//
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// Poll PCIe Link Active status till it is active
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//
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while(LEqual(And(RDCA(NCRN,0x52,0x0,0x0,ROOTPORT_READ),0x2000),0))
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{
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Stall(10)
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}
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}
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//
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// Restore of Remapped Device Link Control's "Active State Link PM Control" field
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//
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RDCA(NCRN,Add(NPCV,0x10),0xFFFFFFFC,And(NEAV,0x0003),ENDPOINT_WRITE)
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//
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// Restore of Remapped Device related device BAR for the MSI-X Table BAR if the device supports unique MSI-X Table BAR
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//
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If(LNotEqual(NMVV,0))
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{
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RDCA(NCRN,NMBV,0x0,NMVV,ENDPOINT_WRITE)
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}
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//
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// Restore of Remapped Device related device BAR for the MSI-X PBA BAR if the device supports unique MSI-X PBA BAR
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//
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If(LNotEqual(NPVV,0))
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{
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RDCA(NCRN,NPBV,0x0,NPVV,ENDPOINT_WRITE)
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}
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//Fix warning: not all control paths return a value
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Return(0)
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}
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Method(_PS3,0,Serialized)
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{
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//
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// Return if RST Pcie Storage Remapping is disabled
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//
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If(LEqual(NITV,0))
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{
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//Fix warning: restricted method should not return a value
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}
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//
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// Store Endpoint CMD and remapped BAR for CNRS() restoration
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//
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Store(RDCA(NCRN,0x4,0x0,0x0,ENDPOINT_READ),PCMD)
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If(LEqual(NITV,1)) // Store BAR5 if Endpoint is AHCI Interface
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{
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Store(0x24,PRBI)
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Store(RDCA(NCRN,0x24,0x0,0x0,ENDPOINT_READ),PRBD)
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}
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ElseIf(LEqual(NITV,2)) // Store BAR0 if Endpoint is NVMe Interface
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{
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Store(0x10,PRBI)
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Store(RDCA(NCRN,0x10,0x0,0x0,ENDPOINT_READ),PRBD)
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}
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EPD3()
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RPD3(NCRN)
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}
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Method(_PS0,0,Serialized)
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{
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//
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// Return if RST Pcie Storage Remapping is disabled
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//
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If(LEqual(NITV,0))
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{
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//Fix warning: restricted method should not return a value
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}
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RPD0(NCRN)
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EPD0()
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//
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// Check NSR bit in PMCS
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// If this bit is 0, invoke CNRS() to perform restoration on the remapped device and hidden root port
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//
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Store(RDCA(NCRN,Add(NPMV,0x04),0x0,0x0,ENDPOINT_READ),Local0)
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If(LEqual(And(Local0,0x8),0))
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{
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CNRS()
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}
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}
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