/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Bit Difinitions
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//
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#ifndef BIT0
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#define BIT0 0x0001
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#define BIT1 0x0002
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#define BIT2 0x0004
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#define BIT3 0x0008
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#define BIT4 0x0010
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#define BIT5 0x0020
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#define BIT6 0x0040
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#define BIT7 0x0080
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#define BIT8 0x0100
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#define BIT9 0x0200
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#endif //BIT0
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//
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// High Definition Audio Controller - Device 31, Function 3
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//
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Scope(\_SB.PC00.CAVS) {
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#ifndef BIT0
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#define BIT0 0x00000001
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#endif
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#ifndef BIT1
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#define BIT1 0x00000002
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#endif
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#ifndef BIT2
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#define BIT2 0x00000004
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#endif
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#ifndef BIT3
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#define BIT3 0x00000008
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#endif
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#ifndef BIT4
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#define BIT4 0x00000010
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#endif
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#ifndef BIT5
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#define BIT5 0x00000020
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#endif
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#ifndef BIT6
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#define BIT6 0x00000040
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#endif
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#ifndef BIT7
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#define BIT7 0x00000080
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#endif
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#ifndef BIT8
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#define BIT8 0x00000100
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#endif
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#ifndef BIT9
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#define BIT9 0x00000200
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#endif
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#ifndef BIT10
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#define BIT10 0x00000400
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#endif
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#ifndef BIT11
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#define BIT11 0x00000800
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#endif
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#ifndef BIT12
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#define BIT12 0x00001000
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#endif
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#ifndef BIT13
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#define BIT13 0x00002000
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#endif
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#ifndef BIT14
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#define BIT14 0x00004000
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#endif
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#ifndef BIT15
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#define BIT15 0x00008000
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#endif
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#ifndef BIT16
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#define BIT16 0x00010000
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#endif
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#ifndef BIT17
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#define BIT17 0x00020000
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#endif
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#ifndef BIT18
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#define BIT18 0x00040000
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#endif
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#ifndef BIT19
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#define BIT19 0x00080000
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#endif
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#ifndef BIT20
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#define BIT20 0x00100000
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#endif
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#ifndef BIT21
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#define BIT21 0x00200000
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#endif
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#ifndef BIT22
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#define BIT22 0x00400000
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#endif
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#ifndef BIT23
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#define BIT23 0x00800000
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#endif
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#ifndef BIT24
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#define BIT24 0x01000000
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#endif
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#ifndef BIT25
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#define BIT25 0x02000000
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#endif
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#ifndef BIT26
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#define BIT26 0x04000000
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#endif
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#ifndef BIT27
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#define BIT27 0x08000000
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#endif
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#ifndef BIT28
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#define BIT28 0x10000000
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#endif
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#ifndef BIT29
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#define BIT29 0x20000000
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#endif
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#ifndef BIT30
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#define BIT30 0x40000000
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#endif
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#ifndef BIT31
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#define BIT31 0x80000000
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#endif
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//
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// Define a Memory Region that will allow access to the HDA PCI Configuration Space
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//
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OperationRegion(HDAR, PCI_Config, 0x00, 0x100)
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Field(HDAR,WordAcc,NoLock,Preserve) {
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VDID,32, // 0x00, VID DID
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Offset(0x48), // 0x48, CGCTL - Clock Gating Control
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,6,
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MBCG,1, // MISCBDCGE [BIT6]
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Offset(0x54), // 0x54, Power Management Control and Status Register
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,8,
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PMEE,1,
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,6,
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PMES,1 // PME Status
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}
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Name(_S0W, 3) // Device can wake itself from D3 in S0
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Method(_DSW, 3) { Store(Arg0, PMEE) } // Device wake enable
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Method(_PRW, 0) { Return(GPRW(0x0D, 4)) } // Can wakeup from S4 state
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// GPE handler for HDA, this is part of _Lxx handler for bus 0 PME
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Method(GPEH) {
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If(LEqual(VDID, 0xFFFFFFFF)) {
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Return()
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}
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If(LAnd(PMEE, PMES)) {
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ADBG("HDAS GPEH")
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Store(1, PMES) // clear PME Status
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Notify(CAVS, 0x02)
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}
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}
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// NHLT Table memory descriptor, returned from _DSM
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Name(NBUF, ResourceTemplate () {
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// NHLT table address (_MIN = NHLT 64bit pointer, _MAX = _MIN + _LEN - 1) and length (_LEN)
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QWordMemory (ResourceConsumer, , MinNotFixed, MaxNotFixed, NonCacheable, ReadOnly,
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0x1, // AddressGranularity
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0x0000000000000000, // AddressMinimum _MIN
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0x0000000000000000, // AddressMaximum _MAX
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0x0,
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0x0, // RangeLength _LEN
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, , NHLT, AddressRangeACPI,)
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})
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Method(AUWA,0,Serialized)
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{
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If(LEqual(PCHS, 1)) {
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If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-H A0 stepping (RevID = 0x0)
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} else {
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If(LEqual(\_SB.PC00.LPC0.CRID, 0x0)) { Return (1) } // Apply to SPT-LP A0 stepping (RevID = 0x0)
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If(LEqual(\_SB.PC00.LPC0.CRID, 0x1)) { Return (1) } // Apply to SPT-LP A1 stepping (RevID = 0x1)
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If(LEqual(\_SB.PC00.LPC0.CRID, 0x9)) { Return (1) } // Apply to SPT-LP A2 stepping (RevID = 0x9)
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}
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Return (0)
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}
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Method(_INI) {
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// Update resource according to NVS
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ADBG("HDAS _INI")
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// Set NHLT base address and length
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CreateQWordField(NBUF, ^NHLT._MIN, NBAS)
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CreateQWordField(NBUF, ^NHLT._MAX, NMAS)
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CreateQWordField(NBUF, ^NHLT._LEN, NLEN)
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Store(NHLA, NBAS)
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Add(NHLA, Subtract(NHLL, 1), NMAS)
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Store(NHLL, NLEN)
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If(LEqual(AUWA(), 1)) {
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Store(0, \_SB.PC00.CAVS.MBCG)
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}
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}
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Method(_DSM, 0x4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgObj}) {
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// Arg0 - UUID: A69F886E-6CEB-4594-A41F-7B5DCE24C553 (Buffer)
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// Arg1 - Revision ID: 0x01 (Integer)
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// Arg2 - Function Index: 0x0 - 0x3 (Integer) - See below for details.
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// Arg3 - Depends on Function Index - See below for details.
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// Return - Depends on Function Index - See below for details.
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ADBG("HDAS _DSM")
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if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,Arg3)) }
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// Verify UUID
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If (LEqual(Arg0, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))) {
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Switch(ToInteger(Arg2)) {
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// Function 0: Function Support Query
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// Arg2 - Function Index: 0x00 (Integer)
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// Arg3: Unused
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// Return: Bitmask of functions supported. (Buffer)
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Case(0) {
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// Supports function 0 - 3
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Return(Buffer(One) { 0x0F })
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}
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// Function 1: Query Non HD Audio Descriptor Table
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// Used by the Intel Offload Engine Driver to discover the
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// non HD Audio devices supported by the Audio DSP.
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// Arg2 - Function Index: 0x01 (Integer)
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// Arg3 - Unused
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// Return - ACPI Table describing the non HD Audio links and devices supported by the ADSP (ResourceBuffer)
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Case(1) {
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ADBG("_DSM Fun 1 NHLT")
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// NBUF - Memory Resource Descriptor buffer with address and length of NHLT
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Return(NBUF)
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}
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// Function 2: Query Feature Mask
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// Used by the Intel Offload Engine Driver to retrieve a bitmask
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// of features allowable on this platform.
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// Arg2 - Function Index: 0x02 (Integer)
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// Arg3: Unused
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// Return: Bitmask of supported features.
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Case (2) {
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ADBG("_DSM Fun 2 FMSK")
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// Bit 0 == '1', WoV is supported, Bit 0 == '0', WoV not supported
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// Bit 1 == '1', BT Sideband is supported, Bit 1 == '0', BT not supported
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// Bit 2 == '1', codec based VAD support allowable
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// Bit 3 - 4 Reserved
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// Bit 5 == '1', BT Intel HFP SCO is supported
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// Bit 6 == '1', BT Intel A2DP is supported
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// Bit 7 == '1', DSP based speech pre-processing disabled
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// Bit 8 == '1', Windows Voice Activation, Bit 8 == '0', Intel Wake on Voice
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// Bit 9 - 31 Reserved, shall be set to '0'
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// ADFM - NVS AudioDSP Feature Bit Mask updated from PchPolicy
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Return(ADFM)
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}
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// Function 3: Query Pre/Post Processing Module Support
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// Used by the Intel Offload Engine Driver to determine if a
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// specified PP Module is allowed to be supported on this platform
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// Arg2 - Function Index: 0x03 (Integer)
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// Arg3 - UUID: Specifies the UUID of the PP module to check (Buffer)
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// Return - TRUE if PP Module supported, else FALSE.
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Case (3) {
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ADBG("_DSM Fun 3 PPMS")
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// ADPM - NVS AudioDSP Post-Processing Module Bit Mask updated from PchPolicy: HdaConfig->DspPpModuleMask
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//
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// Example (to be updated with real GUIDs of supported 3rd party IP):
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//
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// 3rd Party DSP Processing Module 1 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT0)
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// Check PP module with GUID AABBCCDD-EEFF-1122-3344-556677889900
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// If (LEqual(Arg3, ToUUID ("AABBCCDD-EEFF-1122-3344-556677889900"))){
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// Return(And(ADPM, 0x1)) // DspPpModuleMask[BIT0] / ADPM[BIT0] set - supported 3rd Party Processing Module 1(return true)
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// }
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//
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// 3rd Party DSP Processing Module 5 placeholder (enabled by policy HdaConfig->DspPpModuleMask |= BIT5)
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// Check PP module with GUID 11111111-2222-3333-4444-AABBCCDDEEFF
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// If (LEqual(Arg3, ToUUID ("11111111-2222-3333-4444-AABBCCDDEEFF"))){
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// Return(And(ADPM, 0x20)) // DspPpModuleMask[BIT5] / ADPM[BIT5] set - supported 3rd Party Processing Module 5(return true)
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// }
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//
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// Implement for all supported PP modules
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//
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Return(0) // Is not supported
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}
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Default {
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// Function not supported (Arg2)
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ADBG("_DSM Fun NOK")
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Return(Buffer(One) { 0x00 })
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}
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} // Switch(Arg2) End
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} // If(Arg0, UUID) End
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// UUID not supported (Arg0)
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ADBG("_DSM UUID NOK")
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//Fix warning: not all control paths return a value
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Return(0)
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} // _DSM End
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} // end "High Definition Audio Controller"
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