/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPU_PCI_ACCESS_H_
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#define _CPU_PCI_ACCESS_H_
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#include "DataTypes.h"
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//
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// CPU Types; this needs to be contiguous to assist in table look up
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//
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#define MAX_CPU_TYPES 1
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//
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// CPU Index for MC function look-up
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//
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#define MAX_CPU_INDEX 1
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//
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// Box Types; this needs to be contiguous to assist in table look up
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//
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#define BOX_CHA_MISC 0
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#define BOX_CHA_PMA 1
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#define BOX_CHA_CMS 2
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#define BOX_CHABC 3
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#define BOX_PCU 4
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#define BOX_VCU 5
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#define BOX_M2MEM 6
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#define BOX_MC 7
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#define BOX_MCIO 8
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#define BOX_KTI 9
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#define BOX_M3KTI 10
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#define BOX_MCDDC 11
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#define BOX_M2UPCIE 12
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#define BOX_IIO_PCIE_DMI 13
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#define BOX_IIO_PCIE 14
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#define BOX_IIO_PCIE_NTB 15
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#define BOX_IIO_CB 16
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#define BOX_IIO_VTD 17
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#define BOX_IIO_RTO 18
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#define BOX_UBOX 19
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#define BOX_FPGA 20
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#define MAX_BOX_TYPES 21
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//
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// Maximum Number of Instances supported by each box type. Note that if the number of instances
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// are same for all supported CPUs, then we will have only one #define here (i.e MAX_ALL_XXXXX)
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//
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#define MAX_SKX_CHA 28
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#define MAX_SKX_M2PCIE 5
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#define MAX_ALL_CBOBC 1
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#define MAX_SKX_M3KTI 2
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#define MAX_SKX_KTIAGENT 3
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#define MAX_SKX_M2MEM 2
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#define MAX_ALL_M2PCIE 1
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#define MAX_ALL_UBOX 1
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#define MAX_ALL_IIO 4
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#define MAX_ALL_PCU 1
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#define MAX_ALL_VCU 1
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#define MAX_ALL_IIO_CB 1 // 1 instance per CB function block
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#define MAX_ALL_IIO_PCIE_DMI 1 // 0:0:0
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#define MAX_ALL_IIO_PCIE_NTB 3 // 4 instances in PCIE_NTB (0:3:0/1/2/3)
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#define MAX_ALL_IIO_RTO 21 // 4 instances per M/PSTACK + 1 Cstack
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#define MAX_ALL_IIO_RTO_DMI 4 // 4 instances in C stack
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#define MAX_ALL_IIO_RTO_VTD 6 // 6 instances in IIO_RTO block across C/P/MCP stacks
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#define MAX_ALL_IIO_RTO_VTD_DMI 1 // 1 instances in IIO_RTO block across C stack
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#define MAX_ALL_IIO_PCIE 21 // 4 instances per M/PSTACK + 1 Cstack
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#define IIO_RTO 0
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#define IIO_RTO_DMI 1
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#define IIO_RTO_GLOBAL 2
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#define IIO_RTO_GLOBAL_DMI 3
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#define IIO_RTO_VTD 4
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#define IIO_RTO_VTD_DMI 5
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//
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// Format of CSR register offset passed to helper functions.
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// This must be kept in sync with the CSR XML parser tool that generates CSR offset definitions in the CSR header files.
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//
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typedef union {
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struct {
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UINT32 offset : 12; // bits <11:0>
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UINT32 size : 3; // bits <14:12>
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UINT32 pseudo : 1; // bit <15>
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UINT32 funcblk : 8; // bits <23:16>
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UINT32 boxtype : 8; // bits <31:24>
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} Bits;
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UINT32 Data;
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} CSR_OFFSET;
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//
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// Format of CSR register offset passed to helper functions.
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// This must be kept in sync with the CSR XML parser tool that generates CSR offset definitions in the CSR header files.
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//
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#define PCI_REG_ADDR(Bus,Device,Function,Offset) \
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(((Offset) & 0xff) | (((Function) & 0x07) << 8) | (((Device) & 0x1f) << 11) | (((Bus) & 0xff) << 16))
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#define PCIE_REG_ADDR(Bus,Device,Function,Offset) \
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(((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
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#endif // _CPU_PCI_ACCESS_H_
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