/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <SysHost.h>
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#include "PcieAddress.h"
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
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#include <Library/DebugLib.h>
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#endif
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#ifdef _MSC_VER
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#pragma optimize ("",off)
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#endif //_MSC_VER
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//////////////////////////////////////////////////////////////////////////
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//
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// Common Silicon Address Library
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// This Lib provide the way use platform Library instance
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//
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//////////////////////////////////////////////////////////////////////////
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PCIE_MMCFG_TABLE_TYPE mMmcfgTable =\
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{
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{
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{'M', 'C', 'F', 'G'}, // Signature
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0x00000090, // Length
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0x01, // Revision
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0x08, // The Maximum number of Segments
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0x00FF, // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ...
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{{
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0, //MMCFG_BASE_ADDRESS, // Base Address Low
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0x00000000, // Base Address High
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0x0000, // Segment 0
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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}}
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};
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//
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// Segment 1 ~ 7
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//
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PCIE_MMCFG_BASE_ADDRESS_TYPE mMmcfgAddr[] = \
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{
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0001, // Segment 1
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0002, // Segment 2
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0003, // Segment 3
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0004, // Segment 4
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0005, // Segment 5
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0006, // Segment 6
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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},
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{
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0x00000000, // Base Address Low
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0x00000000, // Base Address High
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0x0007, // Segment 7
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0x00, // Start Bus
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0xFF, // End Bus
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{0x00,0x00,0x00,0x00} // Reserved
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}
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};
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/**
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This Lib is used for platfor to set platform specific Pcie MMCFG Table
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@param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type.
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@param NumOfSeg: Sumber of Segments in the table.
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@retval <>NULL The function completed successfully.
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@retval NULL Returen Error
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**/
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UINTN
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SetSocketMmcfgTable (
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IN UINT8 SocketLastBus[],
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IN UINT8 SocketFirstBus[],
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IN UINT8 segmentSocket[],
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IN UINT32 mmCfgBaseH[],
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IN UINT32 mmCfgBaseL[],
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IN UINT8 NumOfSocket
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)
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{
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
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UINT32 MmcfgTableSize;
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PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable;
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UINT8 i, *Dest, *Source;
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union {
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UINT64 D64;
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UINT32 D32[2];
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} Data;
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MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSocket * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE));
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HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr);
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ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr));
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Data.D64 = PcdGet64 (PcdPciExpressBaseAddress);
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mMmcfgTable.MmcfgBase[0].BaseAddressL = Data.D32[0];
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mMmcfgTable.MmcfgBase[0].BaseAddressH = Data.D32[1];
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//1. copy global variable mMcfgTable to HobMmcfgTable
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// note that mMmcfgTable only has PCIE_MMCFG_BASE_ADDRESS_TYPE for segment 0 (for socket 0)
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// need to copy base addresses for other segments corresponding to sockets 1 through NumOfSocket-1
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Dest = (UINT8*)HobMmcfgTable;
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Source = (UINT8*)&mMmcfgTable;
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for(i=0; i<sizeof(PCIE_MMCFG_TABLE_TYPE); i++)
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{
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Dest[i] = Source[i];
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}
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//2. copy remaining segments 1 to NumOfSocket-1 from global array to HobMmcfgTable
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if(NumOfSocket > 1){
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Dest = (UINT8*)&HobMmcfgTable->MmcfgBase[1];
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Source = (UINT8*)&mMmcfgAddr[0];//array of base addresses starting with segment 1 (max segment = 7)
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for(i = 0; i< (MmcfgTableSize - sizeof(PCIE_MMCFG_TABLE_TYPE)); i++){
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Dest[i] = Source[i];
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}
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}
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HobMmcfgTable->Header.Length = MmcfgTableSize;
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for(i=0; i<NumOfSocket; i++)
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{
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HobMmcfgTable->MmcfgBase[i].StartBus = SocketFirstBus[i];
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HobMmcfgTable->MmcfgBase[i].EndBus = SocketLastBus[i];
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HobMmcfgTable->MmcfgBase[i].Segment = segmentSocket[i];
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HobMmcfgTable->MmcfgBase[i].BaseAddressH = mmCfgBaseH[i];
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HobMmcfgTable->MmcfgBase[i].BaseAddressL = mmCfgBaseL[i];
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}
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#endif
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return 0;
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};
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/**
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This Lib is used for platform to set platform specific Pcie MMCFG Table
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@param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type.
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@param NumOfSeg: Sumber of Segments in the table.
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@retval <>NULL The function completed successfully.
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@retval NULL Returen Error
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**/
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UINTN
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EFIAPI
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SetPcieSegMmcfgTable (
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IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable,
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IN UINT32 NumOfSeg
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)
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{
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION) && !defined(SIM_BUILD)
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UINT32 MmcfgTableSize;
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PCIE_MMCFG_TABLE_TYPE *HobMmcfgTable;
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union {
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UINT64 D64;
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UINT32 D32[2];
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} Data;
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Data.D32[0] = Data.D32[1] = 0;
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MmcfgTableSize = sizeof(PCIE_MMCFG_HEADER_TYPE) + (NumOfSeg * sizeof(PCIE_MMCFG_BASE_ADDRESS_TYPE));
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HobMmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr);
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//ASSERT (MmcfgTableSize < PcdGetSize (PcdPcieMmcfgTablePtr));
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//InternalMemCopyMem(HobMmcfgTable, MmcfgTable, PcdGetSize (PcdPcieMmcfgTablePtr));
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MmcfgTable->Header.Length = MmcfgTableSize;
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if((MmcfgTable->MmcfgBase[0].BaseAddressL == 0) && (MmcfgTable->MmcfgBase[0].BaseAddressH == 0))
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{
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//
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// The first time default should be the PcdPciExpressBaseAddress
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//
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Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
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HobMmcfgTable->MmcfgBase[0].BaseAddressL = Data.D32[0];
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HobMmcfgTable->MmcfgBase[0].BaseAddressH = Data.D32[1];
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};
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#endif
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return 0;
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};
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/**
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This Lib return PCIE MMCFG Base Address
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@param Address: A pointer of the address of the Common Address Structure for PCIE type.
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@param Buffer: A pointer of buffer for the value read from platform.
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@retval <>NULL The function completed successfully.
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@retval NULL Returen Error
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**/
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UINTN
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EFIAPI
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GetPcieSegMmcfgBaseAddress (
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IN USRA_ADDRESS *Address
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)
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{
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UINT32 BaseAddressL=0; // Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism
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UINT32 BaseAddressH=0;
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UINTN SegMmcfgBase;
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION)
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PCIE_MMCFG_TABLE_TYPE *MmcfgTable=NULL;
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union {
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UINTN D64;
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UINT32 D32[2];
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} Data;
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#endif
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#if !defined(MINIBIOS_BUILD) && !defined(KTI_SW_SIMULATION)
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if(Address->Attribute.HostPtr == 0) {
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MmcfgTable = (PCIE_MMCFG_TABLE_TYPE *) PcdGetPtr (PcdPcieMmcfgTablePtr);
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if(MmcfgTable->Header.Length != 0)
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{
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BaseAddressH = MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressH;
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BaseAddressL = MmcfgTable->MmcfgBase[Address->Pcie.Seg].BaseAddressL;
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} else {
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//
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// if it is not valid MMCFG pointer, initialize it to use the predefined default MMCFG Table
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//
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SetPcieSegMmcfgTable(&mMmcfgTable, PcdGet32 (PcdNumOfPcieSeg));
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BaseAddressH = mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddressH;
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BaseAddressL = mMmcfgTable.MmcfgBase[Address->Pcie.Seg].BaseAddressL;
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if((BaseAddressL == 0) && (BaseAddressH == 0)){
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Data.D32[0] = Data.D32[1] = 0;
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Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
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BaseAddressL = Data.D32[0];
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BaseAddressH = Data.D32[1];
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}
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}
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}
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else
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#endif
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{
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BaseAddressH = 0;
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BaseAddressL = 0;
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}
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if((BaseAddressL == 0) && (BaseAddressH == 0))
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{
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#if defined(MINIBIOS_BUILD) || defined(KTI_SW_SIMULATION)
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BaseAddressL = 0x80000000;
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BaseAddressH = 0;
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#else
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//
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// The first time default should be the PcdPciExpressBaseAddress
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//
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Data.D32[0] = Data.D32[1] = 0;
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Data.D64 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
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BaseAddressL = Data.D32[0];
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BaseAddressH = Data.D32[1];
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#endif
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}
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return SegMmcfgBase = BaseAddressL;
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};
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