/** @file
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Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _CPUCSRACCESS_PROTOCOL_H_
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#define _CPUCSRACCESS_PROTOCOL_H_
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//
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// CPU CSR Access Protocol GUID
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//
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// {0067835F-9A50-433a-8CBB-852078197814}
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#define EFI_CPU_CSR_ACCESS_GUID \
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{ \
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0x67835f, 0x9a50, 0x433a, 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 \
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}
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//#define REG_ADDR( bus, dev, func, reg, size ) ((size << 28) + ((bus+2) << 20) + (dev << 15) + (func << 12) + reg)
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typedef
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UINT64
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(EFIAPI *GET_CPU_CSR_ADDRESS) (
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IN UINT8 SocId,
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IN UINT8 BoxInst,
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IN UINT32 Offset,
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IN OUT UINT8 *Size
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);
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typedef
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UINT32
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(EFIAPI *READ_CPU_CSR) (
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IN UINT8 SocId,
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IN UINT8 BoxInst,
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IN UINT32 Offset
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);
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typedef
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VOID
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(EFIAPI *WRITE_CPU_CSR) (
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IN UINT8 SocId,
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IN UINT8 BoxInst,
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IN UINT32 RegOffset,
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IN UINT32 Data
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);
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typedef
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UINT32
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(EFIAPI *READ_MC_CPU_CSR) (
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IN UINT8 SocId,
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IN UINT8 McId,
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IN UINT32 Offset
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);
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typedef
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VOID
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(EFIAPI *WRITE_MC_CPU_CSR) (
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IN UINT8 SocId,
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IN UINT8 McId,
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IN UINT32 RegOffset,
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IN UINT32 Data
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);
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typedef
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UINTN
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(EFIAPI *GET_MC_CPU_ADDR) (
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IN UINT8 SocId,
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IN UINT8 McId,
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IN UINT32 RegOffset
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);
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typedef
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UINT32
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(EFIAPI *READ_PCI_CSR) (
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IN UINT8 socket,
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IN UINT32 reg
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);
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typedef
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VOID
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(EFIAPI *WRITE_PCI_CSR) (
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IN UINT8 socket,
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IN UINT32 reg,
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IN UINT32 data
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);
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typedef
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UINT32
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(EFIAPI *GET_PCI_CSR_ADDR) (
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IN UINT8 socket,
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IN UINT32 reg
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);
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typedef
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VOID
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(EFIAPI *UPDATE_CPU_CSR_ACCESS_VAR) (
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VOID
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);
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typedef
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UINT32
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(EFIAPI *BIOS_2_PCODE_MAILBOX_WRITE) (
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IN UINT8 socket,
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IN UINT32 command,
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IN UINT32 data
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);
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typedef
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UINT64
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(EFIAPI *BIOS_2_VCODE_MAILBOX_WRITE) (
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IN UINT8 socket,
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IN UINT32 command,
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IN UINT32 data
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);
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typedef
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VOID
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(EFIAPI *BREAK_AT_CHECK_POINT) (
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IN UINT8 majorCode,
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IN UINT8 minorCode,
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IN UINT16 data
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);
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typedef struct _EFI_CPU_CSR_ACCESS_PROTOCOL {
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GET_CPU_CSR_ADDRESS GetCpuCsrAddress;
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READ_CPU_CSR ReadCpuCsr;
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WRITE_CPU_CSR WriteCpuCsr;
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BIOS_2_PCODE_MAILBOX_WRITE Bios2PcodeMailBoxWrite;
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BIOS_2_VCODE_MAILBOX_WRITE Bios2VcodeMailBoxWrite;
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READ_MC_CPU_CSR ReadMcCpuCsr;
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WRITE_MC_CPU_CSR WriteMcCpuCsr;
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GET_MC_CPU_ADDR GetMcCpuCsrAddress;
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UPDATE_CPU_CSR_ACCESS_VAR UpdateCpuCsrAccessVar;
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READ_PCI_CSR ReadPciCsr;
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WRITE_PCI_CSR WritePciCsr;
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GET_PCI_CSR_ADDR GetPciCsrAddress;
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BREAK_AT_CHECK_POINT BreakAtCheckpoint;
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} EFI_CPU_CSR_ACCESS_PROTOCOL;
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extern EFI_GUID gEfiCpuCsrAccessGuid;
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#endif
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