/** @file
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Copies the memory related timing and configuration information into the
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Compatible BIOS data (BDAT) table.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _MrcRmtData_h_
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#define _MrcRmtData_h_
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#include "MrcTypes.h"
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#define VDD_1_350 1350 ///< VDD in millivolts
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#define VDD_1_500 1500 ///< VDD in millivolts
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#define PI_STEP_BASE 2048 ///< Magic number from spec
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#define PI_STEP_INTERVAL 128 ///< tCK is split into this amount of intervals
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#define PI_STEP ((PI_STEP_BASE) / (PI_STEP_INTERVAL))
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#define VREF_STEP_BASE 100 ///< Magic number from spec
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#define TX_VREF_STEP 7800 ///< TX Vref step in microvolts
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#define TX_VREF(VDD) (((TX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
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#define RX_VREF_STEP 8000 ///< TX Vref step in microvolts
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#define RX_VREF(VDD) (((RX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
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#define CA_VREF_STEP 8000 ///< TX Vref step in microvolts
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#define CA_VREF(VDD) (((CA_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)) ///< VDD passed in is in millivolts
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#define MAX_SPD_RMT 512 ///< The maximum amount of data, in bytes, in an SPD structure.
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#define RMT_PRIMARY_VERSION 4 ///< The BDAT structure that is currently supported.
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#define RMT_SECONDARY_VERSION 0 ///< The BDAT structure that is currently supported.
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#define MAX_MODE_REGISTER 7 ///< Number of mode registers
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#define MAX_DRAM_DEVICE 9 ///< Maximum number of memory devices
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//
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// Warning: Bdat4.h has its own copy of this #define
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// make sure to change it in both places
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//
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#define MAX_SCHEMA_LIST_LENGTH (10)
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/*
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Memory Schema GUID
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This is private GUID used by MemoryInit internally.
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{CE3F6794-4883-492C-8DBA-2FC098447710}
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*/
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#ifdef BDAT_SUPPORT
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extern EFI_GUID gEfiMemorySchemaGuid;
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#endif
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/*
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GUID for Schema List HOB
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This is private GUID used by MemoryInit internally.
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{3047C2AC-5E8E-4C55-A1CB-EAAD0A88861B}
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*/
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extern EFI_GUID gMrcSchemaListHobGuid;
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#pragma pack(push, 1)
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typedef struct {
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UINT8 RxDqLeft; ///< Units = piStep
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UINT8 RxDqRight;
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UINT8 TxDqLeft;
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UINT8 TxDqRight;
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UINT8 RxVrefLow; ///< Units = rxVrefStep
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UINT8 RxVrefHigh;
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UINT8 TxVrefLow; ///< Units = txVrefStep
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UINT8 TxVrefHigh;
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} BDAT_DQ_MARGIN_STRUCTURE;
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typedef struct {
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UINT8 RxDqLeft; ///< Units = piStep
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UINT8 RxDqRight;
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UINT8 TxDqLeft;
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UINT8 TxDqRight;
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UINT8 CmdLeft;
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UINT8 CmdRight;
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UINT8 RecvenLeft; ///< Units = recvenStep
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UINT8 RecvenRight;
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UINT8 WrLevelLeft; ///< Units = wrLevelStep
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UINT8 WrLevelRight;
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UINT8 RxVrefLow; ///< Units = rxVrefStep
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UINT8 RxVrefHigh;
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UINT8 TxVrefLow; ///< Units = txVrefStep
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UINT8 TxVrefHigh;
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UINT8 CmdVrefLow; ///< Units = caVrefStep
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UINT8 CmdVrefHigh;
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} BDAT_RANK_MARGIN_STRUCTURE;
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typedef struct {
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UINT16 RecEnDelay[MAX_STROBE];
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UINT16 WlDelay[MAX_STROBE];
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UINT8 RxDqDelay[MAX_STROBE];
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UINT8 TxDqDelay[MAX_STROBE];
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UINT8 ClkDelay;
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UINT8 CtlDelay;
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UINT8 CmdDelay[3];
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UINT8 IoLatency;
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UINT8 Roundtrip;
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} BDAT_RANK_TRAINING_STRUCTURE;
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typedef struct {
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UINT16 ModeRegister[MAX_MODE_REGISTER]; ///< Mode register settings
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} BDAT_DRAM_MRS_STRUCTURE;
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typedef struct {
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UINT8 RankEnabled; ///< 0 = Rank disabled
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UINT8 RankMarginEnabled; ///< 0 = Rank margin disabled
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UINT8 DqMarginEnabled; ///< 0 = Dq margin disabled
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BDAT_RANK_MARGIN_STRUCTURE RankMargin; ///< Rank margin data
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BDAT_DQ_MARGIN_STRUCTURE DqMargin[MAX_DQ]; ///< Array of Dq margin data per rank
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BDAT_RANK_TRAINING_STRUCTURE RankTraining; ///< Rank training settings
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BDAT_DRAM_MRS_STRUCTURE RankMRS[MAX_DRAM_DEVICE]; ///< Rank MRS settings
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} BDAT_RANK_STRUCTURE;
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typedef struct {
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UINT8 SpdValid[MAX_SPD_RMT / (CHAR_BITS * sizeof (UINT8))]; ///< Each valid bit maps to SPD byte
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UINT8 SpdData[MAX_SPD_RMT]; ///< Array of raw SPD data bytes
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} BDAT_SPD_STRUCTURE;
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typedef struct {
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UINT8 DimmEnabled; ///< 0 = DIMM disabled
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BDAT_RANK_STRUCTURE RankList[MAX_RANK_IN_DIMM]; ///< Array of ranks per DIMM
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BDAT_SPD_STRUCTURE SpdBytes; ///< SPD data per DIMM
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} BDAT_DIMM_STRUCTURE;
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typedef struct {
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UINT8 ChannelEnabled; ///< 0 = Channel disabled
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UINT8 NumDimmSlot; ///< Number of slots per channel on the board
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BDAT_DIMM_STRUCTURE DimmList[MAX_DIMMS_IN_CHANNEL]; ///< Array of DIMMs per channel
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} BDAT_CHANNEL_STRUCTURE;
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typedef struct {
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UINT8 ControllerEnabled; ///< 0 = MC disabled
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UINT16 ControllerDeviceId; ///< MC device Id
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UINT8 ControllerRevisionId; ///< MC revision Id
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UINT16 MemoryFrequency; ///< Memory frequency in units of MHz / 10
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///< e.g. ddrFreq = 13333 for tCK = 1.5 ns
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UINT16 MemoryVoltage; ///< Memory Vdd in units of mV
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///< e.g. ddrVoltage = 1350 for Vdd = 1.35 V
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UINT8 PiStep; ///< Step unit = piStep * tCK / 2048
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///< e.g. piStep = 16 for step = 11.7 ps (1/128 tCK)
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UINT16 RxVrefStep; ///< Step unit = rxVrefStep * Vdd / 100
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///< e.g. rxVrefStep = 520 for step = 7.02 mV
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UINT16 TxVrefStep; ///< Step unit = txVrefStep * Vdd / 100
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UINT16 CaVrefStep; ///< Step unit = caVrefStep * Vdd / 100
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UINT8 RecvenStep; ///< Step unit = recvenStep * tCK / 2048
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UINT8 WrLevelStep; ///< Step unit = wrLevelStep * tCK / 2048
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BDAT_CHANNEL_STRUCTURE ChannelList[MAX_CHANNEL]; ///< Array of channels per memory controller
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} BDAT_SOCKET_STRUCTURE;
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typedef struct {
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union {
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UINT32 Data32; ///< MRC version: Major.Minor.Revision.Build
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struct {
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UINT8 Build; ///< MRC version: Build
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UINT8 Revision; ///< MRC version: Revision
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UINT8 Minor; ///< MRC version: Minor
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UINT8 Major; ///< MRC version: Major
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} Version;
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} RefCodeRevision; ///< Major.Minor.Revision.Build
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UINT8 MaxController; ///< Max controllers per system, e.g. 1
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UINT8 MaxChannel; ///< Max channels per memory controller, e.g. 2
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UINT8 MaxDimm; ///< Max DIMM per channel, e.g. 2
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UINT8 MaxRankDimm; ///< Max ranks per DIMM, e.g. 2
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UINT8 MaxStrobe; ///< Number of Dqs used by the rank, e.g. 18
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UINT8 MaxDq; ///< Number of Dq bits used by the rank, e.g. 72
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UINT32 MarginLoopCount; ///< Units of cache line
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BDAT_SOCKET_STRUCTURE ControllerList[MAX_CONTROLLERS]; ///< Array of memory controllers per system
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} BDAT_SYSTEM_STRUCTURE;
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typedef struct {
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UINT32 Data1;
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UINT16 Data2;
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UINT16 Data3;
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UINT8 Data4[8];
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} BDAT_EFI_GUID;
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typedef struct {
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UINT16 HobType;
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UINT16 HobLength;
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UINT32 Reserved;
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} BDAT_HOB_GENERIC_HEADER;
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typedef struct {
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BDAT_HOB_GENERIC_HEADER Header;
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BDAT_EFI_GUID Name;
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///
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/// Guid specific data goes here
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///
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} BDAT_HOB_GUID_TYPE;
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typedef struct {
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BDAT_EFI_GUID SchemaId; ///< The GUID uniquely identifies the format of the data contained within the structure.
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UINT32 DataSize; ///< The total size of the memory block, including both the header as well as the schema specific data.
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UINT16 Crc16; ///< Crc16 is computed in the same manner as the field in the BDAT_HEADER_STRUCTURE.
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} MRC_BDAT_SCHEMA_HEADER_STRUCTURE;
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typedef struct {
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MRC_BDAT_SCHEMA_HEADER_STRUCTURE SchemaHeader; ///< The schema header.
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union {
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UINT32 Data; ///< MRC version: Major.Minor.Revision.Build
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struct {
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UINT8 Build; ///< MRC version: Build
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UINT8 Revision; ///< MRC version: Revision
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UINT8 Minor; ///< MRC version: Minor
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UINT8 Major; ///< MRC version: Major
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} Version;
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} RefCodeRevision; ///< Major.Minor.Revision.Build
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UINT8 MaxController; ///< Max controllers per system, e.g. 1
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UINT8 MaxChannel; ///< Max channels per memory controller, e.g. 2
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UINT8 MaxDimm; ///< Max DIMM per channel, e.g. 2
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UINT8 MaxRankDimm; ///< Max ranks per DIMM, e.g. 2
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UINT8 MaxStrobe; ///< Number of Dqs used by the rank, e.g. 18
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UINT8 MaxDq; ///< Number of Dq bits used by the rank, e.g. 72
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UINT32 MarginLoopCount; ///< Units of cache line
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BDAT_SOCKET_STRUCTURE ControllerList[MAX_CONTROLLERS]; ///< Array of memory controllers per system
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} BDAT_MEMORY_DATA_STRUCTURE;
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typedef struct {
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BDAT_HOB_GUID_TYPE HobGuidType;
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BDAT_MEMORY_DATA_STRUCTURE MemorySchema;
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} BDAT_MEMORY_DATA_HOB;
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#pragma pack (pop)
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typedef struct {
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BDAT_HOB_GUID_TYPE HobGuidType;
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UINT16 SchemaHobCount;
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UINT16 Reserved;
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BDAT_EFI_GUID SchemaHobGuids[MAX_SCHEMA_LIST_LENGTH];
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} MRC_BDAT_SCHEMA_LIST_HOB;
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#endif //_MrcRmtData_h_
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