/** @file
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PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PchSpi.h"
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//
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// Global variables
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//
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GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance;
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//
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// mPchSpiResvMmioAddr keeps the reserved MMIO range assiged to SPI.
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// In SMM it always set back the reserved MMIO address to SPI BAR0 to ensure the MMIO range
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// won't overlap with SMRAM range, and trusted.
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//
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GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr;
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/**
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<b>SPI Runtime SMM Module Entry Point</b>\n
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- <b>Introduction</b>\n
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The SPI SMM module provide a standard way for other modules to use the PCH SPI Interface in SMM.
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- @pre
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- EFI_SMM_BASE2_PROTOCOL
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- Documented in System Management Mode Core Interface Specification .
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- @result
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The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @endlink with GUID
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gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver.
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- <b>Integration Check List</b>\n
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- This driver supports Descriptor Mode only.
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- This driver supports Hardware Sequence only.
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- When using SMM SPI Protocol to perform flash access in an SMI handler,
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and the SMI occurrence is asynchronous to normal mode code execution,
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proper synchronization mechanism must be applied, e.g. disable SMI before
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the normal mode SendSpiCmd() starts and re-enable SMI after
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the normal mode SendSpiCmd() completes.
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@note The implementation of SendSpiCmd() uses GBL_SMI_EN in
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SMI_EN register (ABase + 30h) to disable and enable SMIs. But this may
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not be effective as platform may well set the SMI_LOCK bit (i.e., PMC PCI Offset A0h [4]).
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So the synchronization at caller level is likely needed.
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@param[in] ImageHandle Image handle of this driver.
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@param[in] SystemTable Global system service table.
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@retval EFI_SUCCESS Initialization complete.
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@exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
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@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
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@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
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**/
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EFI_STATUS
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EFIAPI
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InstallPchSpi (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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//
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// Init PCH spi reserved MMIO address.
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//
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mSpiResvMmioAddr = PCH_SPI_BASE_ADDRESS;
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///
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/// Allocate pool for SPI protocol instance
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///
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Status = gSmst->SmmAllocatePool (
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EfiRuntimeServicesData, /// MemoryType don't care
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sizeof (SPI_INSTANCE),
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(VOID **) &mSpiInstance
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);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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if (mSpiInstance == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
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///
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/// Initialize the SPI protocol instance
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///
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Status = SpiProtocolConstructor (mSpiInstance);
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if (EFI_ERROR (Status)) {
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return Status;
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}
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///
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/// Install the SMM PCH_SPI_PROTOCOL interface
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///
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Status = gSmst->SmmInstallProtocolInterface (
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&(mSpiInstance->Handle),
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&gPchSmmSpiProtocolGuid,
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EFI_NATIVE_INTERFACE,
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&(mSpiInstance->SpiProtocol)
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);
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if (EFI_ERROR (Status)) {
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gSmst->SmmFreePool (mSpiInstance);
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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/**
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Acquire PCH spi mmio address.
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It is not expected for this BAR0 to change because the SPI device is hidden
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from the OS for SKL PCH LP/H B stepping and above (refer to section 3.5.1),
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but if it is ever different from the preallocated address, reassign it back.
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In SMM, it always override the BAR0 and returns the reserved MMIO range for SPI.
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@param[in] SpiInstance Pointer to SpiInstance to initialize
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@retval PchSpiBar0 return SPI MMIO address
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**/
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UINTN
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AcquireSpiBar0 (
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IN SPI_INSTANCE *SpiInstance
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)
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{
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UINT32 SpiBar0;
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//
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// Save original SPI physical MMIO address
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//
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SpiBar0 = MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & ~(B_PCH_SPI_BAR0_MASK);
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if (SpiBar0 != mSpiResvMmioAddr) {
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//
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// Temporary disable MSE, and override with SPI reserved MMIO address, then enable MSE.
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//
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MmioAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
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MmioWrite32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0, mSpiResvMmioAddr);
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MmioOr8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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}
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//
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// SPIBAR0 will be different before and after PCI enum so need to get it from SPI BAR0 reg.
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//
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return mSpiResvMmioAddr;
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}
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/**
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Release pch spi mmio address. Do nothing.
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@param[in] SpiInstance Pointer to SpiInstance to initialize
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@retval None
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**/
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VOID
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ReleaseSpiBar0 (
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IN SPI_INSTANCE *SpiInstance
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)
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{
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}
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/**
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This function is a hook for Spi to disable BIOS Write Protect
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@retval EFI_SUCCESS The protocol instance was properly initialized
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@retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
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**/
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EFI_STATUS
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EFIAPI
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DisableBiosWriteProtect (
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VOID
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)
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{
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UINTN SpiBaseAddress;
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SpiBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI
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);
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// Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
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//
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MmioOr8 (
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SpiBaseAddress + R_PCH_SPI_BC + 1,
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(B_PCH_SPI_BC_SYNC_SS >> 8)
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);
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///
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/// Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
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/// Enable the access to the BIOS space for both read and write cycles
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///
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MmioOr8 (
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SpiBaseAddress + R_PCH_SPI_BC,
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B_PCH_SPI_BC_WPD
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);
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///
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/// PCH BIOS Spec Section 3.7 BIOS Region SMM Protection Enabling
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/// If the following steps are implemented:
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/// - Set the EISS bit (SPI PCI Offset DCh [5]) = 1b
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/// - Follow the 1st recommendation in section 3.6
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/// the BIOS Region can only be updated by following the steps bellow:
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/// - Once all threads enter SMM
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/// - Read memory location FED30880h OR with 00000001h, place the result in EAX,
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/// and write data to lower 32 bits of MSR 1FEh (sample code available)
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/// - Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
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/// - Modify BIOS Region
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/// - Clear BIOSWE bit (SPI PCI Offset DCh [0]) = 0b
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///
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if ((MmioRead8 (SpiBaseAddress + R_PCH_SPI_BC) & B_PCH_SPI_BC_EISS) != 0) {
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CpuSmmDisableBiosWriteProtect ();
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}
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return EFI_SUCCESS;
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}
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/**
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This function is a hook for Spi to enable BIOS Write Protect
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**/
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VOID
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EFIAPI
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EnableBiosWriteProtect (
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VOID
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)
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{
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UINTN SpiBaseAddress;
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SpiBaseAddress = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI
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);
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///
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/// Clear BIOSWE bit (SPI PCI Offset DCh [0]) = 0b
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/// Disable the access to the BIOS space for write cycles
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///
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MmioAnd8 (
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SpiBaseAddress + R_PCH_SPI_BC,
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(UINT8) (~B_PCH_SPI_BC_WPD)
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);
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///
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/// Check if EISS bit is set
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///
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if (((MmioRead8 (SpiBaseAddress + R_PCH_SPI_BC)) & B_PCH_SPI_BC_EISS) == B_PCH_SPI_BC_EISS) {
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CpuSmmEnableBiosWriteProtect ();
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}
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}
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