/** @file
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This is the driver that publishes the SMM Control Protocol.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "SmmControlDriver.h"
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STATIC SMM_CONTROL_PRIVATE_DATA mSmmControl;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mABase;
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VOID
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EFIAPI
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DisablePendingSmis (
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VOID
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);
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/**
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Fixup internal data pointers so that the services can be called in virtual mode.
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@param[in] Event The event registered.
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@param[in] Context Event context.
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**/
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VOID
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EFIAPI
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SmmControlVirtualAddressChangeEvent (
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IN EFI_EVENT Event,
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IN VOID *Context
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)
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{
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gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl.SmmControl.Trigger));
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gRT->ConvertPointer (EFI_INTERNAL_POINTER, (VOID *) &(mSmmControl.SmmControl.Clear));
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}
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/**
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<b>SmmControl DXE RUNTIME Module Entry Point</b>\n
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- <b>Introduction</b>\n
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The SmmControl module is a DXE RUNTIME driver that provides a standard way
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for other drivers to trigger software SMIs.
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- @pre
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- PCH Power Management I/O space base address has already been programmed.
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If SmmControl Runtime DXE driver is run before Status Code Runtime Protocol
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is installed and there is the need to use Status code in the driver, it will
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be necessary to add EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID to the dependency file.
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- EFI_SMM_BASE2_PROTOCOL
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- Documented in the System Management Mode Core Interface Specification.
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- @result
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The SmmControl driver produces the EFI_SMM_CONTROL_PROTOCOL documented in
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System Management Mode Core Interface Specification.
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@param[in] ImageHandle Handle for the image of this driver
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@param[in] SystemTable Pointer to the EFI System Table
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@retval EFI_STATUS Results of the installation of the SMM Control Protocol
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**/
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EFI_STATUS
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EFIAPI
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SmmControlDriverEntryInit (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_EVENT Event;
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DEBUG ((DEBUG_INFO, "SmmControlDriverEntryInit() Start\n"));
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///
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/// Get the Power Management I/O space base address. We assume that
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/// this base address has already been programmed if this driver is
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/// being run.
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///
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PchAcpiBaseGet (&mABase);
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Status = EFI_SUCCESS;
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if (mABase != 0) {
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///
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/// Install the instance of the protocol
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///
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mSmmControl.Signature = SMM_CONTROL_PRIVATE_DATA_SIGNATURE;
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mSmmControl.Handle = ImageHandle;
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mSmmControl.SmmControl.Trigger = Activate;
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mSmmControl.SmmControl.Clear = Deactivate;
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mSmmControl.SmmControl.MinimumTriggerPeriod = 0;
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///
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/// Install our protocol interfaces on the device's handle
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///
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Status = gBS->InstallMultipleProtocolInterfaces (
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&mSmmControl.Handle,
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&gEfiSmmControl2ProtocolGuid,
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&mSmmControl.SmmControl,
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NULL
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);
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} else {
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Status = EFI_DEVICE_ERROR;
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return Status;
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}
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Status = gBS->CreateEventEx (
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EVT_NOTIFY_SIGNAL,
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TPL_NOTIFY,
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SmmControlVirtualAddressChangeEvent,
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NULL,
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&gEfiEventVirtualAddressChangeGuid,
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&Event
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);
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///
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/// Disable any PCH SMIs that, for whatever reason, are asserted after the boot.
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///
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DisablePendingSmis ();
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DEBUG ((DEBUG_INFO, "SmmControlDriverEntryInit() End\n"));
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return Status;
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}
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/**
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Trigger the software SMI
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@param[in] Data The value to be set on the software SMI data port
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@retval EFI_SUCCESS Function completes successfully
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**/
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EFI_STATUS
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EFIAPI
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SmmTrigger (
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IN UINT8 Data
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)
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{
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UINT32 OutputData;
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UINT32 OutputPort;
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///
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/// Enable the APMC SMI
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///
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OutputPort = mABase + R_PCH_SMI_EN;
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OutputData = IoRead32 ((UINTN) OutputPort);
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OutputData |= (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);
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DEBUG (
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(DEBUG_EVENT,
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"The SMI Control Port at address %x will be written to %x.\n",
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OutputPort,
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OutputData)
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);
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IoWrite32 (
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(UINTN) OutputPort,
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(UINT32) (OutputData)
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);
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OutputPort = R_PCH_APM_CNT;
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OutputData = Data;
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///
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/// Generate the APMC SMI
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///
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IoWrite8 (
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(UINTN) OutputPort,
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(UINT8) (OutputData)
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);
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return EFI_SUCCESS;
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}
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/**
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Clear the SMI status
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@retval EFI_SUCCESS The function completes successfully
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@retval EFI_DEVICE_ERROR Something error occurred
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**/
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EFI_STATUS
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EFIAPI
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SmmClear (
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VOID
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)
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{
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EFI_STATUS Status;
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UINT32 OutputData;
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UINT32 OutputPort;
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Status = EFI_SUCCESS;
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///
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/// Clear the Power Button Override Status Bit, it gates EOS from being set.
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///
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OutputPort = mABase + R_PCH_ACPI_PM1_STS;
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OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR;
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DEBUG (
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(DEBUG_EVENT,
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"The PM1 Status Port at address %x will be written to %x.\n",
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OutputPort,
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OutputData)
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);
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IoWrite16 (
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(UINTN) OutputPort,
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(UINT16) (OutputData)
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);
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///
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/// Clear the APM SMI Status Bit
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///
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OutputPort = mABase + R_PCH_SMI_STS;
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OutputData = B_PCH_SMI_STS_APM;
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DEBUG (
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(DEBUG_EVENT,
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"The SMI Status Port at address %x will be written to %x.\n",
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OutputPort,
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OutputData)
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);
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IoWrite32 (
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(UINTN) OutputPort,
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(UINT32) (OutputData)
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);
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///
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/// Set the EOS Bit
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///
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OutputPort = mABase + R_PCH_SMI_EN;
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OutputData = IoRead32 ((UINTN) OutputPort);
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OutputData |= B_PCH_SMI_EN_EOS;
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DEBUG (
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(DEBUG_EVENT,
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"The SMI Control Port at address %x will be written to %x.\n",
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OutputPort,
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OutputData)
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);
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IoWrite32 (
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(UINTN) OutputPort,
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(UINT32) (OutputData)
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);
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///
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/// There is no need to read EOS back and check if it is set.
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/// This can lead to a reading of zero if an SMI occurs right after the SMI_EN port read
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/// but before the data is returned to the CPU.
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/// SMM Dispatcher should make sure that EOS is set after all SMI sources are processed.
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///
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return Status;
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}
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/**
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This routine generates an SMI
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@param[in] This The EFI SMM Control protocol instance
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@param[in, out] CommandPort The buffer contains data to the command port
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@param[in, out] DataPort The buffer contains data to the data port
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@param[in] Periodic Periodic or not
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@param[in] ActivationInterval Interval of periodic SMI
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@retval EFI Status Describing the result of the operation
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@retval EFI_INVALID_PARAMETER Some parameter value passed is not supported
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**/
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EFI_STATUS
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EFIAPI
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Activate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL * This,
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IN OUT UINT8 *CommandPort OPTIONAL,
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IN OUT UINT8 *DataPort OPTIONAL,
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IN BOOLEAN Periodic OPTIONAL,
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IN UINTN ActivationInterval OPTIONAL
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)
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{
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EFI_STATUS Status;
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UINT8 Data;
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if (Periodic) {
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DEBUG ((DEBUG_WARN, "Invalid parameter\n"));
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return EFI_INVALID_PARAMETER;
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}
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if (CommandPort == NULL) {
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Data = 0xFF;
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} else {
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Data = *CommandPort;
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}
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///
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/// Clear any pending the APM SMI
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///
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Status = SmmClear ();
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if (EFI_ERROR (Status)) {
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return Status;
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}
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return SmmTrigger (Data);
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}
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/**
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This routine clears an SMI
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@param[in] This The EFI SMM Control protocol instance
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@param[in] Periodic Periodic or not
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@retval EFI Status Describing the result of the operation
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@retval EFI_INVALID_PARAMETER Some parameter value passed is not supported
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**/
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EFI_STATUS
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EFIAPI
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Deactivate (
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IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,
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IN BOOLEAN Periodic OPTIONAL
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)
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{
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if (Periodic) {
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return EFI_INVALID_PARAMETER;
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}
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return SmmClear ();
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}
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/**
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Disable all pending SMIs
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**/
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VOID
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EFIAPI
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DisablePendingSmis (
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VOID
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)
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{
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UINT32 Data;
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UINT32 Port;
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BOOLEAN SciEn;
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///
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/// Determine whether an ACPI OS is present (via the SCI_EN bit)
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///
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Port = mABase + R_PCH_ACPI_PM1_CNT;
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Data = IoRead16 ((UINTN) Port);
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SciEn = (BOOLEAN) ((Data & B_PCH_ACPI_PM1_CNT_SCI_EN) == B_PCH_ACPI_PM1_CNT_SCI_EN);
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if (!SciEn) {
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///
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/// Clear any SMIs that double as SCIs (when SCI_EN==0)
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///
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Port = mABase + R_PCH_ACPI_PM1_STS;
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Data = 0xFFFF;
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IoWrite16 ((UINTN) Port, (UINT16) (Data));
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Port = mABase + R_PCH_ACPI_PM1_EN;
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Data = 0x0000;
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IoWrite16 ((UINTN) Port, (UINT16) (Data));
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Port = mABase + R_PCH_ACPI_PM1_CNT;
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Data = 0x0000;
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IoWrite16 ((UINTN) Port, (UINT16) (Data));
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Port = mABase + R_PCH_ACPI_GPE0_STS_127_96;
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Data = (UINT32) ~B_PCH_ACPI_GPE0_STS_127_96_WADT;
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IoWrite32 ((UINTN) Port, (UINT32) (Data));
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Port = mABase + R_PCH_ACPI_GPE0_EN_127_96;
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Data = B_PCH_ACPI_GPE0_EN_127_96_WADT;
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IoWrite32 ((UINTN) Port, (UINT32) (Data));
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}
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///
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/// Clear and disable all SMIs that are unaffected by SCI_EN
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///
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GpioDisableAllGpiSmi ();
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GpioClearAllGpiSmiSts ();
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Port = mABase + R_PCH_DEVACT_STS;
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Data = 0xFFFF;
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IoWrite32 ((UINTN) Port, (UINT32) (Data));
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Port = mABase + R_PCH_SMI_STS;
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Data = 0xFFFFFFFF;
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IoWrite32 ((UINTN) Port, (UINT32) (Data));
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///
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/// (Make sure to write this register last -- EOS re-enables SMIs for the PCH)
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///
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Port = mABase + R_PCH_SMI_EN;
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Data = IoRead32 ((UINTN) Port);
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///
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/// clear all bits except those tied to SCI_EN
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///
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Data &= B_PCH_SMI_EN_BIOS_RLS;
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///
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/// enable SMIs and specifically enable writes to APM_CNT.
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///
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Data |= B_PCH_SMI_EN_GBL_SMI | B_PCH_SMI_EN_APMC;
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///
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/// NOTE: Default value of EOS is set in PCH, it will be automatically cleared Once the PCH asserts SMI# low,
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/// we don't need to do anything to clear it
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///
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IoWrite32 ((UINTN) Port, (UINT32) (Data));
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}
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