/** @file
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File to contain all the hardware specific stuff for the Smm Sx dispatch protocol.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PchSmmHelpers.h"
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#define PROGRESS_CODE_S3_SUSPEND_END PcdGet32 (PcdProgressCodeS3SuspendEnd)
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GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC SX_SOURCE_DESC = {
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PCH_SMM_NO_FLAGS,
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{
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{
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{
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ACPI_ADDR_TYPE,
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{R_PCH_SMI_EN}
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},
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S_PCH_SMI_EN,
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N_PCH_SMI_EN_ON_SLP_EN
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},
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NULL_BIT_DESC_INITIALIZER
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},
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{
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{
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{
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ACPI_ADDR_TYPE,
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{R_PCH_SMI_STS}
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},
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S_PCH_SMI_STS,
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N_PCH_SMI_STS_ON_SLP_EN
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}
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},
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{
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{
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ACPI_ADDR_TYPE,
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{R_PCH_SMI_STS}
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},
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S_PCH_SMI_STS,
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N_PCH_SMI_STS_ON_SLP_EN
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}
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};
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/**
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Get the Sleep type
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@param[in] Record No use
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@param[out] Context The context that includes SLP_TYP bits to be filled
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**/
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VOID
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EFIAPI
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SxGetContext (
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IN DATABASE_RECORD *Record,
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OUT PCH_SMM_CONTEXT *Context
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)
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{
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UINT32 Pm1Cnt;
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Pm1Cnt = IoRead32 ((UINTN) (mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT));
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///
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/// By design, the context phase will always be ENTRY
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///
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Context->Sx.Phase = SxEntry;
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///
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/// Map the PM1_CNT register's SLP_TYP bits to the context type
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///
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switch (Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) {
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case V_PCH_ACPI_PM1_CNT_S0:
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Context->Sx.Type = SxS0;
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break;
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case V_PCH_ACPI_PM1_CNT_S1:
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Context->Sx.Type = SxS1;
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break;
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case V_PCH_ACPI_PM1_CNT_S3:
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Context->Sx.Type = SxS3;
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break;
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case V_PCH_ACPI_PM1_CNT_S4:
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Context->Sx.Type = SxS4;
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break;
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case V_PCH_ACPI_PM1_CNT_S5:
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Context->Sx.Type = SxS5;
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break;
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default:
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ASSERT (FALSE);
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break;
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}
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}
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/**
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Check whether sleep type of two contexts match
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@param[in] Context1 Context 1 that includes sleep type 1
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@param[in] Context2 Context 2 that includes sleep type 2
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@retval FALSE Sleep types match
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@retval TRUE Sleep types don't match
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**/
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BOOLEAN
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EFIAPI
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SxCmpContext (
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IN PCH_SMM_CONTEXT *Context1,
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IN PCH_SMM_CONTEXT *Context2
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)
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{
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return (BOOLEAN) (Context1->Sx.Type == Context2->Sx.Type);
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}
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/**
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For each PCIE RP clear PME SCI status and disable SCI, then PCIEXP_WAKE_STS from PMC.
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This prevents platform from waking more than one time due to a single PCIE wake event.
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Normally it's up to OS to clear SCI statuses. But in a scenario where platform wakes
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and goes to S5 instead of booting to OS, the SCI status would remain set and would trigger another wake.
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**/
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VOID
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ClearPcieSci (
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VOID
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)
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{
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UINT32 MaxPorts;
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UINT32 RpIndex;
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UINTN RpBase;
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MaxPorts = GetPchMaxPciePortNum ();
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for (RpIndex = 0; RpIndex < MaxPorts; RpIndex++) {
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RpBase = PchPcieBase (RpIndex);
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if (MmioRead16 (RpBase + PCI_VENDOR_ID_OFFSET) != 0xFFFF) {
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MmioAnd8 ((RpBase + R_PCH_PCIE_MPC + 3), (UINT8)~((UINT8)(B_PCH_PCIE_MPC_PMCE >> 24)));
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MmioWrite32 (RpBase + R_PCH_PCIE_SMSCS, B_PCH_PCIE_SMSCS_PMCS);
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}
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}
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IoWrite16 (mAcpiBaseAddr + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PCIEXP_WAKE_STS);
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}
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/**
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When we get an SMI that indicates that we are transitioning to a sleep state,
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we need to actually transition to that state. We do this by disabling the
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"SMI on sleep enable" feature, which generates an SMI when the operating system
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tries to put the system to sleep, and then physically putting the system to sleep.
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**/
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VOID
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PchSmmSxGoToSleep (
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VOID
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)
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{
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UINT32 Pm1Cnt;
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UINT32 PchPwrmBase;
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ClearPcieSci ();
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PchPwrmBaseGet (&PchPwrmBase);
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///
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/// Flush cache into memory before we go to sleep. It is necessary for S3 sleep
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/// because we may update memory in SMM Sx sleep handlers -- the updates are in cache now
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///
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AsmWbinvd ();
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///
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/// Disable SMIs
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///
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PchSmmClearSource (&SX_SOURCE_DESC);
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PchSmmDisableSource (&SX_SOURCE_DESC);
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///
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/// Get Power Management 1 Control Register Value
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///
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Pm1Cnt = IoRead32 ((UINTN) (mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT));
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///
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/// Record S3 suspend performance data
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///
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if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S3) {
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///
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/// Report status code before goto S3 sleep
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///
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REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PROGRESS_CODE_S3_SUSPEND_END);
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///
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/// Flush cache into memory before we go to sleep.
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///
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AsmWbinvd ();
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}
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///
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/// Now that SMIs are disabled, write to the SLP_EN bit again to trigger the sleep
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///
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Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SLP_EN;
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IoWrite32 ((UINTN) (mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT), Pm1Cnt);
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///
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/// Should only proceed if wake event is generated.
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///
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if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SLP_TYP) == V_PCH_ACPI_PM1_CNT_S1) {
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while (((IoRead16 ((UINTN) (mAcpiBaseAddr + R_PCH_ACPI_PM1_STS))) & B_PCH_ACPI_PM1_STS_WAK) == 0x0);
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} else {
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CpuDeadLoop ();
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}
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///
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/// The system just went to sleep. If the sleep state was S1, then code execution will resume
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/// here when the system wakes up.
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///
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Pm1Cnt = IoRead32 ((UINTN) (mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT));
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if ((Pm1Cnt & B_PCH_ACPI_PM1_CNT_SCI_EN) == 0) {
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///
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/// An ACPI OS isn't present, clear the sleep information
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///
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Pm1Cnt &= ~B_PCH_ACPI_PM1_CNT_SLP_TYP;
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Pm1Cnt |= V_PCH_ACPI_PM1_CNT_S0;
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IoWrite32 ((UINTN) (mAcpiBaseAddr + R_PCH_ACPI_PM1_CNT), Pm1Cnt);
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}
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PchSmmClearSource (&SX_SOURCE_DESC);
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PchSmmEnableSource (&SX_SOURCE_DESC);
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}
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