/** @file
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PCH Port 61h bit-4 toggling in SMM IO Trap
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PchInitSmm.h"
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpu; ///< To read and write save state
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GLOBAL_REMOVE_IF_UNREFERENCED EFI_HANDLE mPchIoTrapHandle; ///< Pause and resume via EFI_HANDLE
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *mPchSmmIoTrapControl; ///< To pause and resume IO trap
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GLOBAL_REMOVE_IF_UNREFERENCED UINTN mInternalState = 0; ///< To store the toggle value for each CPU threads
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/**
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This SMI handle will pause the IO trap in the beginning
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@param[in] DispatchHandle - The handle of this callback, obtained when registering
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@param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT
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@retval None
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**/
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VOID
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PchIoTrapPort61hSmiCallback (
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IN EFI_HANDLE DispatchHandle,
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IN CONST VOID *CallbackContext,
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IN OUT VOID *CommBuffer,
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IN OUT UINTN *CommBufferSize
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)
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{
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EFI_STATUS Status;
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UINTN CpuIndex;
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UINTN Mask;
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UINT8 ReadValue, WriteValue;
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EFI_SMM_SAVE_STATE_IO_INFO IoInfo;
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//
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// Disabling the IO Trap, prevent SMI re-enter because of reading port 61h in handler itself
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//
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Status = mPchSmmIoTrapControl->Pause (
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mPchSmmIoTrapControl,
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mPchIoTrapHandle
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Detects the CPU which causes the IO Trap
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//
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for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
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Status = mSmmCpu->ReadSaveState (
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mSmmCpu,
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sizeof (EFI_SMM_SAVE_STATE_IO_INFO),
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EFI_SMM_SAVE_STATE_REGISTER_IO,
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CpuIndex,
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&IoInfo
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);
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if (Status == EFI_SUCCESS) {
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//
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// Make sure the IO trap is byte read, port input only, and it is port 0x61
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//
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if ((IoInfo.IoWidth == EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8) &&
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(IoInfo.IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&
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(IoInfo.IoPort == 0x61)) {
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//
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// Read from Port 61h, toggle bit4 based on the internal state
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//
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ReadValue = IoRead8 (0x61);
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Mask = (UINTN) (1 << CpuIndex);
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mInternalState ^= Mask;
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WriteValue = (mInternalState & Mask) ? (ReadValue | 0x10) : (ReadValue & ~0x10);
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Status = mSmmCpu->WriteSaveState (
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mSmmCpu,
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sizeof (UINT8),
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EFI_SMM_SAVE_STATE_REGISTER_RAX,
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CpuIndex,
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&WriteValue
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);
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ASSERT_EFI_ERROR (Status);
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} //if the iotrap is the one we want
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} //if iotrap happens for this thread
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} //for (iterate for all threads)
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//
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// Resume the IO Trap
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// Port 61h bit-4 emulation will be disabled after exit boot service
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// The disabling mechanism is actually to not resume the trap.
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// This means, even after exit boot service, this handler will be called once
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// before it is disabled
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//
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if (mPchNvsArea->ExitBootServicesFlag == 0) {
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Status = mPchSmmIoTrapControl->Resume (
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mPchSmmIoTrapControl,
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mPchIoTrapHandle
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);
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ASSERT_EFI_ERROR (Status);
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} else {
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DEBUG ((DEBUG_INFO, "Port61H trap has been disabled. \n"));
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}
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}
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/**
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Locate required protocol and register the IO trap in this entry point
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@param[in] ImageHandle - Handle for the image of this driver
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@param[in] SystemTable - Pointer to the EFI System Table
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@retval EFI_SUCCESS - PCH SMM handler was installed
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**/
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EFI_STATUS
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EFIAPI
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InstallIoTrapPort61h (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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EFI_SMM_IO_TRAP_REGISTER_CONTEXT PchIoTrapContext;
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DEBUG ((DEBUG_INFO, "InstallIoTrapPort61h()\n"));
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if (mPchConfigHob->Port61hSmm.Enable == 0) {
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return EFI_SUCCESS;
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}
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//
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// Locate the protocol to read and write save state
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//
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Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOID **) &mSmmCpu);
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ASSERT_EFI_ERROR (Status);
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//
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// Locate the protocol for pause and resume
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//
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Status = gSmst->SmmLocateProtocol (&gPchSmmIoTrapControlGuid, NULL, (VOID **) &mPchSmmIoTrapControl);
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ASSERT_EFI_ERROR (Status);
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//
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// Configure trap type, in ECP, MergeDisable should be TRUE for pause and resume to work
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//
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PchIoTrapContext.Type = ReadTrap;
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PchIoTrapContext.Length = 1;
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PchIoTrapContext.Address = 0x61;
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Status = mPchIoTrap->Register (
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mPchIoTrap,
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(EFI_SMM_HANDLER_ENTRY_POINT2) PchIoTrapPort61hSmiCallback,
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&PchIoTrapContext,
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&mPchIoTrapHandle
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);
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ASSERT_EFI_ERROR (Status);
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return EFI_SUCCESS;
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}
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