/** @file
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PCH Pcie SMM Driver Entry
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PchInitSmm.h"
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE *mDevAspmOverride;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mNumOfDevAspmOverride;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolicyRevision;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchBusNumber;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mTempRootPortBusNumMin;
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GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mTempRootPortBusNumMax;
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_ROOT_PORT_CONFIG mPcieRootPortConfig[PCH_MAX_PCIE_ROOT_PORTS];
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GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mLtrNonSupportRpBitMap;
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GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mPciePmTrapExecuted = FALSE;
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GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mAllowNoLtrIccPllShutdownPolicy = FALSE;
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extern EFI_GUID gPchDeviceTableHobGuid;
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/**
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Program Common Clock and ASPM of Downstream Devices
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@param[in] PortIndex Pcie Root Port Number
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@param[in] RpDevice Pcie Root Pci Device Number
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@param[in] RpFunction Pcie Root Pci Function Number
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@retval EFI_SUCCESS Root port complete successfully
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@retval EFI_UNSUPPORTED PMC has invalid vendor ID
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**/
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EFI_STATUS
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PchPcieSmi (
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IN UINT8 PortIndex,
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IN UINT8 RpDevice,
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IN UINT8 RpFunction
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)
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{
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UINT8 SecBus;
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UINT8 SubBus;
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EFI_HANDLE Handle;
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UINT32 PwrmBase;
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UINTN RpBase;
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BOOLEAN LtrSupported;
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BOOLEAN DownstreamDevicePresent;
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Handle = NULL;
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LtrSupported = TRUE;
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RpBase = MmPciBase (
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mPchBusNumber,
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(UINT32) RpDevice,
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(UINT32) RpFunction
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);
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if (MmioRead16 (RpBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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return EFI_SUCCESS;
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}
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//
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// Check for presence detect state
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//
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DownstreamDevicePresent = !!(MmioRead16 (RpBase + R_PCH_PCIE_SLSTS) & B_PCIE_SLSTS_PDS);
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mLtrNonSupportRpBitMap &= ~(1 << PortIndex);
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if (DownstreamDevicePresent) {
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SecBus = MmioRead8 (RpBase + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);
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SubBus = MmioRead8 (RpBase + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);
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ASSERT (SecBus != 0 && SubBus != 0);
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PchPcieInitRootPortDownstreamDevices (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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RpDevice,
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RpFunction,
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mTempRootPortBusNumMin,
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mTempRootPortBusNumMax,
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(BOOLEAN)mPcieRootPortConfig[PortIndex].EnableCpm
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);
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if (!LtrSupported) {
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mLtrNonSupportRpBitMap |= 1 << PortIndex;
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}
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//
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// Perform Equalization
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//
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MmioOr32 (RpBase + R_PCH_PCIE_EX_LCTL3, B_PCIE_EX_LCTL3_PE);
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MmioOr32 (RpBase + R_PCH_PCIE_LCTL, B_PCIE_LCTL_RL);
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}
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//
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// If not all devices support LTR, set PWRMBASE + 0x3EC [24,16] = 0, 1
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// This will disable ICC PLL shutdown
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//
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if (!mAllowNoLtrIccPllShutdownPolicy) {
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PchPwrmBaseGet (&PwrmBase);
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if (mLtrNonSupportRpBitMap != 0) {
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MmioAndThenOr32 (PwrmBase + R_PCH_PWRM_CS_SD_CTL2, (UINT32) ~BIT24, BIT16);
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} else {
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MmioAnd32 (PwrmBase + R_PCH_PWRM_CS_SD_CTL2, (UINT32) ~(BIT24 | BIT16));
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}
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}
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return EFI_SUCCESS;
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}
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/**
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PCIE Hotplug SMI call back function for each Root port
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@param[in] DispatchHandle Handle of this dispatch function
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@param[in] RpContext Rootport context, which contains RootPort Index,
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and RootPort PCI BDF.
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**/
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VOID
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EFIAPI
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PchPcieSmiRpHandlerFunction (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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)
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{
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PchPcieSmi (RpContext->RpIndex, RpContext->DevNum, RpContext->FuncNum);
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}
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/**
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PCIE Link Active State Change Hotplug SMI call back function for all Root ports
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@param[in] DispatchHandle Handle of this dispatch function
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@param[in] RpContext Rootport context, which contains RootPort Index,
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and RootPort PCI BDF.
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**/
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VOID
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EFIAPI
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PchPcieLinkActiveStateChange (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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)
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{
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return;
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}
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/**
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PCIE Link Equalization Request SMI call back function for all Root ports
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@param[in] DispatchHandle Handle of this dispatch function
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@param[in] RpContext Rootport context, which contains RootPort Index,
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and RootPort PCI BDF.
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**/
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VOID
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EFIAPI
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PchPcieLinkEqHandlerFunction (
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IN EFI_HANDLE DispatchHandle,
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IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
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)
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{
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///
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/// From PCI Express specification, the PCIe device can request for Link Equalization. When the
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/// Link Equalization is requested by the device, an SMI will be generated by PCIe RP when
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/// enabled and the SMI subroutine would invoke the Software Preset/Coefficient Search
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/// software to re-equalize the link.
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///
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return;
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}
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/**
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An IoTrap callback to config PCIE power management settings
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**/
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VOID
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PchPciePmIoTrapSmiCallback (
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VOID
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)
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{
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UINT32 PwrmBase;
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UINT32 PortIndex;
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UINTN RpBase;
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BOOLEAN L1SubstatesSupportedPerPort;
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UINT8 MaxPciePortNum;
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UINTN RpDevice;
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UINTN RpFunction;
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PCH_GENERATION PchGen;
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PCH_SERIES PchSeries;
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PCH_STEPPING PchStep;
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PchGen = GetPchGeneration ();
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PchSeries = GetPchSeries ();
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PchStep = PchStepping ();
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L1SubstatesSupportedPerPort = FALSE;
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MaxPciePortNum = GetPchMaxPciePortNum ();
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//
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// Step 4a
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// In case not all devices support LTR, disable ICC PLL shutdown
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// set PWRMBASE + 0x3EC [24,16] = 0, 1
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// (Note this register should be saved and restored during S3 transitions)
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//
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if (!mAllowNoLtrIccPllShutdownPolicy) {
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PchPwrmBaseGet (&PwrmBase);
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MmioAndThenOr32 (PwrmBase + R_PCH_PWRM_CS_SD_CTL2, (UINT32) ~BIT24, BIT16);
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}
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for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
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GetPchPcieRpDevFun (PortIndex, &RpDevice, &RpFunction);
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RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
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}
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//
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// Step 4b
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// By this time, LTR support map is known.
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// If all devices support LTR, allow ICC PLL shutdown
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// (Note this register should be saved and restored during S3 transitions)
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//
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if (!mAllowNoLtrIccPllShutdownPolicy) {
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if (mLtrNonSupportRpBitMap == 0) {
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PchPwrmBaseGet (&PwrmBase);
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MmioAnd32 (PwrmBase + R_PCH_PWRM_CS_SD_CTL2, (UINT32) ~(BIT24 | BIT16));
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}
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}
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//
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// Program the remapped root port's ASPM based on endpoint's ASPM
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//
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if ((PchGen == SklPch) &&
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(((PchSeries == PchLp) && (PchStep < PchLpC0)) ||
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((PchSeries == PchH) && (PchStep < PchHD0)))) {
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return;
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}
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}
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/**
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An IoTrap callback to config PCIE power management settings
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@param[in] DispatchHandle - The handle of this callback, obtained when registering
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@param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CALLBACK_CONTEXT
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**/
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VOID
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EFIAPI
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PchPcieIoTrapSmiCallback (
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IN EFI_HANDLE DispatchHandle,
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IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
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IN OUT VOID *CommBuffer,
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IN OUT UINTN *CommBufferSize
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)
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{
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if (CallbackContext->WriteData == PciePmTrap) {
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if (mPciePmTrapExecuted == FALSE) {
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PchPciePmIoTrapSmiCallback ();
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mPciePmTrapExecuted = TRUE;
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}
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} else {
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ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
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}
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}
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/**
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This function clear the Io trap executed flag before enter S3
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@param[in] Handle Handle of the callback
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@param[in] Context The dispatch context
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@retval EFI_SUCCESS PCH register saved
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**/
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EFI_STATUS
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EFIAPI
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PchPcieS3EntryCallBack (
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IN EFI_HANDLE Handle,
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IN CONST VOID *Context OPTIONAL,
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IN OUT VOID *CommBuffer OPTIONAL,
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IN OUT UINTN *CommBufferSize OPTIONAL
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)
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{
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mPciePmTrapExecuted = FALSE;
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return EFI_SUCCESS;
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}
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/**
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Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling
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@param[in] ImageHandle The image handle of this module
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@param[in] SystemTable The EFI System Table
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@retval EFI_SUCCESS The function completes successfully
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**/
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EFI_STATUS
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EFIAPI
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InitializePchPcieSmm (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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UINT8 PortIndex;
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UINT8 Data8;
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UINT32 Data32Or;
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UINT32 Data32And;
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UINTN RpBase;
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UINTN RpDevice;
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UINTN RpFunction;
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EFI_HANDLE PcieHandle;
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PCH_PCIE_SMI_DISPATCH_PROTOCOL *PchPcieSmiDispatchProtocol;
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EFI_HOB_GUID_TYPE* Hob;
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UINT32 DevTableSize;
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EFI_HANDLE PchIoTrapHandle;
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EFI_SMM_IO_TRAP_REGISTER_CONTEXT PchIoTrapContext;
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EFI_SMM_SX_REGISTER_CONTEXT SxDispatchContext;
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PCH_PCIE_IOTRAP_PROTOCOL *PchPcieIoTrapProtocol;
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EFI_HANDLE SxDispatchHandle;
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UINT8 MaxPciePortNum;
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DEBUG ((DEBUG_INFO, "InitializePchPcieSmm () Start\n"));
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MaxPciePortNum = GetPchMaxPciePortNum ();
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//
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// Locate Pch Pcie Smi Dispatch Protocol
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//
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Status = gSmst->SmmLocateProtocol (&gPchPcieSmiDispatchProtocolGuid, NULL, (VOID**)&PchPcieSmiDispatchProtocol);
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ASSERT_EFI_ERROR (Status);
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mPolicyRevision = mSiConfigHob->Header.Revision;
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mPchBusNumber = DEFAULT_PCI_BUS_NUMBER_PCH;
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mTempRootPortBusNumMin = mSiConfigHob->TempPciBusMin;
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mTempRootPortBusNumMax = mSiConfigHob->TempPciBusMax;
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mAllowNoLtrIccPllShutdownPolicy = (BOOLEAN) mPchConfigHob->PcieRp.AllowNoLtrIccPllShutdown;
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ASSERT (sizeof mPcieRootPortConfig == sizeof mPchConfigHob->PcieRp.RootPort);
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CopyMem (
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mPcieRootPortConfig,
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&(mPchConfigHob->PcieRp.RootPort),
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sizeof (mPcieRootPortConfig)
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);
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mDevAspmOverride = NULL;
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mNumOfDevAspmOverride = 0;
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mLtrNonSupportRpBitMap = 0;
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Hob = GetFirstGuidHob (&gPchDeviceTableHobGuid);
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if (Hob != NULL) {
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DevTableSize = GET_GUID_HOB_DATA_SIZE (Hob);
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ASSERT ((DevTableSize % sizeof (PCH_PCIE_DEVICE_OVERRIDE)) == 0);
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mNumOfDevAspmOverride = DevTableSize / sizeof (PCH_PCIE_DEVICE_OVERRIDE);
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DEBUG ((DEBUG_INFO, "Found PcieDeviceTable HOB (%d entries)\n", mNumOfDevAspmOverride));
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Status = gSmst->SmmAllocatePool (
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EfiRuntimeServicesData,
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DevTableSize,
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(VOID **) &mDevAspmOverride
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);
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CopyMem (mDevAspmOverride, GET_GUID_HOB_DATA (Hob), DevTableSize);
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}
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//
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// Throught all PCIE root port function and register the SMI Handler for enabled ports.
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//
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for (PortIndex = 0; PortIndex < MaxPciePortNum; PortIndex++) {
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GetPchPcieRpDevFun (PortIndex, &RpDevice, &RpFunction);
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RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction);
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//
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// Skip the root port function which is not enabled
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//
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if (MmioRead32 (RpBase) == 0xFFFFFFFF) {
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continue;
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}
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if (!mPcieRootPortConfig[PortIndex].EnableHotplugSmi) {
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continue;
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}
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//
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// Register SMI Handlers for Hot Plug and Link Active State Change
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//
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Data8 = MmioRead8 (RpBase + R_PCH_PCIE_SLCAP);
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if (Data8 & B_PCIE_SLCAP_HPC) {
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PcieHandle = NULL;
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Status = PchPcieSmiDispatchProtocol->HotPlugRegister (
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PchPcieSmiDispatchProtocol,
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PchPcieSmiRpHandlerFunction,
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PortIndex,
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&PcieHandle
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);
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ASSERT_EFI_ERROR (Status);
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Status = PchPcieSmiDispatchProtocol->LinkActiveRegister (
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PchPcieSmiDispatchProtocol,
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PchPcieLinkActiveStateChange,
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PortIndex,
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&PcieHandle
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);
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ASSERT_EFI_ERROR (Status);
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Data32Or = B_PCH_PCIE_MPC_HPME;
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Data32And = (UINT32) ~B_PCH_PCIE_MPC_HPME;
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S3BootScriptSaveMemReadWrite (
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S3BootScriptWidthUint32,
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(UINTN) (RpBase + R_PCH_PCIE_MPC),
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&Data32Or, /// Data to be ORed
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&Data32And /// Data to be ANDed
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);
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}
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//
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// Register SMI Handler for Link Equalization Request from Gen 3 Devices.
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//
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Data8 = MmioRead8 (RpBase + R_PCH_PCIE_LCAP);
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if ((Data8 & B_PCIE_LCAP_MLS) == V_PCIE_LCAP_MLS_GEN3) {
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Status = PchPcieSmiDispatchProtocol->LinkEqRegister (
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PchPcieSmiDispatchProtocol,
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PchPcieLinkEqHandlerFunction,
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PortIndex,
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&PcieHandle
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);
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ASSERT_EFI_ERROR (Status);
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}
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}
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ASSERT_EFI_ERROR (Status);
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PchIoTrapContext.Type = WriteTrap;
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PchIoTrapContext.Length = 4;
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PchIoTrapContext.Address = 0;
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Status = mPchIoTrap->Register (
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mPchIoTrap,
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(EFI_SMM_HANDLER_ENTRY_POINT2) PchPcieIoTrapSmiCallback,
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&PchIoTrapContext,
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&PchIoTrapHandle
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);
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ASSERT_EFI_ERROR (Status);
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//
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// Install the PCH Pcie IoTrap protocol
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//
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(gBS->AllocatePool) (EfiBootServicesData, sizeof (PCH_PCIE_IOTRAP_PROTOCOL), (VOID **)&PchPcieIoTrapProtocol);
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PchPcieIoTrapProtocol->PcieTrapAddress = PchIoTrapContext.Address;
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Status = gBS->InstallMultipleProtocolInterfaces (
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&ImageHandle,
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&gPchPcieIoTrapProtocolGuid,
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PchPcieIoTrapProtocol,
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NULL
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);
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//
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// Register the callback for S3 entry
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//
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SxDispatchContext.Type = SxS3;
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SxDispatchContext.Phase = SxEntry;
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Status = mSxDispatch->Register (
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mSxDispatch,
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PchPcieS3EntryCallBack,
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&SxDispatchContext,
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&SxDispatchHandle
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);
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ASSERT_EFI_ERROR (Status);
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DEBUG ((DEBUG_INFO, "InitializePchPcieSmm () End\n"));
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return EFI_SUCCESS;
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}
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