/** @file
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Header file for PCH Initialization Driver.
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Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_INITIALIZATION_DRIVER_H_
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#define _PCH_INITIALIZATION_DRIVER_H_
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typedef UINT16 STRING_REF;
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#ifdef FSP_FLAG
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#include <Library/PeiServicesLib.h>
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#include <Uefi/UefiSpec.h>
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#endif
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Protocol/DriverSupportedEfiVersion.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/PchP2sbLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchEspiLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/TraceHubInitLib.h>
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#include <Guid/EventGroup.h>
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#include <Library/S3BootScriptLib.h>
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#include <Protocol/PciIo.h>
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#include <Protocol/PciPlatform.h>
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#include <Protocol/PciEnumerationComplete.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Library/HobLib.h>
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#include <Library/UefiLib.h>
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#include <Library/MemoryAllocationLib.h>
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#ifndef FSP_FLAG
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#include <Library/DxeServicesTableLib.h>
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#endif
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#include <PchAccess.h>
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#include <SiConfigHob.h>
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#include <Protocol/PchInfo.h>
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#include <IndustryStandard/Pci30.h>
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#include <Library/AslUpdateLib.h>
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#include <Library/MmPciLib.h>
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#include <Library/CpuPlatformLib.h>
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#include <Protocol/BlockIo.h>
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#include <Protocol/PchEmmcTuning.h>
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#include <Library/GpioLib.h>
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#include <Library/GpioNativeLib.h>
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#include <Protocol/PchNvs.h>
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#include <Protocol/PcieIoTrap.h>
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#include <Library/PchInitCommonLib.h>
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#include <Library/PchPciExpressHelpersLib.h>
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#include <Library/PchPsfLib.h>
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#include <Library/PchPsfPrivateLib.h>
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#include <PchConfigHob.h>
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typedef struct {
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PCH_INFO_PROTOCOL PchInfo;
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} PCH_INSTANCE_PRIVATE_DATA;
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//
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// This struct is used to record the fields that is required to be saved and restored during RST PCIe Storage Remapping Configuration
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//
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typedef struct {
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UINT8 PmCapPtr;
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UINT8 PcieCapPtr;
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UINT16 L1ssCapPtr;
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UINT8 EndpointL1ssControl2;
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UINT32 EndpointL1ssControl1;
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UINT16 LtrCapPtr;
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UINT32 EndpointLtrData;
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UINT16 EndpointLctlData16;
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UINT16 EndpointDctlData16;
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UINT16 EndpointDctl2Data16;
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UINT16 RootPortDctl2Data16;
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} PCH_RST_PCIE_STORAGE_SAVE_RESTORE;
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//
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// This struct is used to record the result of RST PCIe Storage detection for each RST PCIe Storage Cycle Router supported on the platform
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//
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typedef struct {
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BOOLEAN SupportRstPcieStoragRemapping; // Indicates if RST PCIe Storage Remapping is supported and PCIe storage device is found under a Cycle Router
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UINT8 RootPortNum; // Indicates the root port number with RST PCIe Storage Remapping remapping supported and PCIe storage device plugged on, numbering is 0-based
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UINT8 RootPortLane; // Indicates the root port lanes occupied by the PCIe storage device with 4-bit mask
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UINT8 DeviceInterface; // Indicates the interface of the PCIe storage device (AHCI or NVMe)
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UINT8 IsMsixSupported; // Indicates if the PCIe storage device support MSI-X cap
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UINT16 MsixStartingVector; // Records the starting vector of PCIe storage device's MSI-X (if supported)
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UINT16 MsixEndingVector; // Records the ending vector of PCIe storage device's MSI-X (if supported)
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UINT32 EndPointBarSize; // Records the PCIe storage device's BAR size
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UINT32 EndPointUniqueMsixTableBar; // Records the PCIe storage device's MSI-X Table BAR if it supports unique MSI-X Table BAR
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UINT32 EndPointUniqueMsixTableBarValue; // Records the PCIe storage device's MSI-X Table BAR value if it supports unique MSI-X Table BAR
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UINT32 EndPointUniqueMsixPbaBar; // Records the PCIe storage device's MSI-X PBA BAR if it supports unique MSI-X PBA BAR
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UINT32 EndPointUniqueMsixPbaBarValue; // Records the PCIe storage device's MSI-X PBA BAR value if it supports unique MSI-X PBA BAR
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UINT8 EndPointBcc; // Records the PCIe storage device's Base Class Code
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UINT8 EndPointScc; // Records the PCIe storage device's Sub Class Code
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UINT8 EndPointPi; // Records the PCIe storage device's Programming Interface
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PCH_RST_PCIE_STORAGE_SAVE_RESTORE PchRstPcieStorageSaveRestore; // Records the fields that is required to be saved and restored
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} PCH_RST_PCIE_STORAGE_DETECTION;
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//
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// Data definitions
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//
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extern EFI_HANDLE mImageHandle;
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//
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// Pch NVS area definition
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//
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extern PCH_NVS_AREA_PROTOCOL mPchNvsAreaProtocol;
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extern PCH_CONFIG_HOB *mPchConfigHob;
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extern SI_CONFIG_HOB *mSiConfigHob;
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//
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// Function Prototype
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//
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//
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// Local function prototypes
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//
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/**
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Initialize the PCH device according to the PCH Policy HOB
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and install PCH info instance.
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**/
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VOID
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InitializePchDevice (
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VOID
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);
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/**
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Common PchInit Module Entry Point
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**/
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VOID
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PchInitEntryPointCommon (
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VOID
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);
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/**
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Common PCH initialization on PCI enumeration complete.
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**/
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VOID
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PchOnPciEnumCompleteCommon (
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VOID
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);
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/**
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Configures Serial IO Controllers
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**/
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EFI_STATUS
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ConfigureSerialIoAtBoot (
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VOID
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);
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/**
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Creates device handles for SerialIo devices in ACPI mode
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**/
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VOID
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CreateSerialIoHandles (
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VOID
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);
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/**
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Mark memory used by SerialIo devices in ACPI mode as allocated
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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AllocateSerialIoMemory (
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VOID
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);
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/**
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Update ASL definitions for SerialIo devices.
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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UpdateSerialIoAcpiData (
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VOID
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);
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/**
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Initialize PCIE SRC clocks in ICC subsystem
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@param[in] GbePortNumber Number of PCIE rootport assigned to GbE adapter
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**/
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VOID
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ConfigurePchPcieClocks (
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IN UINTN GbePortNumber
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);
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/**
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Initialize Intel High Definition Audio ACPI Tables
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_LOAD_ERROR ACPI table cannot be installed
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@retval EFI_UNSUPPORTED ACPI table not set because DSP is disabled
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**/
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EFI_STATUS
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PchHdAudioAcpiInit (
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VOID
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);
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/**
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Configure eMMC in HS400 Mode
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@param[in] This A pointer to PCH_EMMC_TUNING_PROTOCOL structure
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@param[in] Revision Revision parameter used to verify the layout of EMMC_INFO and TUNINGDATA.
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@param[in] EmmcInfo A pointer to EMMC_INFO structure
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@param[out] EmmcTuningData A pointer to EMMC_TUNING_DATA structure
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_NOT_FOUND The item was not found
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@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
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@retval EFI_INVALID_PARAMETER A parameter was incorrect.
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@retval EFI_DEVICE_ERROR Hardware Error
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@retval EFI_NO_MEDIA No media
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@retval EFI_MEDIA_CHANGED Media Change
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@retval EFI_BAD_BUFFER_SIZE Buffer size is bad
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@retval EFI_CRC_ERROR Command or Data CRC Error
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**/
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EFI_STATUS
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EFIAPI
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ConfigureEmmcHs400Mode (
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IN PCH_EMMC_TUNING_PROTOCOL *This,
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IN UINT8 Revision,
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IN EMMC_INFO *EmmcInfo,
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OUT EMMC_TUNING_DATA *EmmcTuningData
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);
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/**
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Install PCH EMMC TUNING PROTOCOL
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**/
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VOID
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InstallPchEmmcTuningProtocol (
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VOID
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);
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/**
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Perform the remaining configuration on PCH SATA to perform device detection,
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then set the SATA SPD and PxE corresponding, and set the Register Lock on PCH SATA
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@retval None
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**/
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VOID
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ConfigurePchSataOnEndOfDxe (
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VOID
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);
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/**
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Update ASL data for CIO2 Device.
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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UpdateCio2AcpiData (
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VOID
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);
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/**
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Initialize Pch acpi
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@param[in] ImageHandle Handle for the image of this driver
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
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**/
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EFI_STATUS
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EFIAPI
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PchAcpiInit (
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IN EFI_HANDLE ImageHandle
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);
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/**
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Update ASL object before Boot
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@retval EFI_STATUS
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@retval EFI_NOT_READY The Acpi protocols are not ready.
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**/
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EFI_STATUS
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PchUpdateNvsArea (
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VOID
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);
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/**
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Initialize PCH Nvs Area opeartion region.
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@retval EFI_SUCCESS initialized successfully
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@retval EFI_NOT_FOUND Nvs Area operation region is not found
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**/
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EFI_STATUS
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PatchPchNvsAreaAddress (
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VOID
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);
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/**
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PCH Update NvsArea ExitBootServicesFlag on ExitBootService. This event is used if only ExitBootService is used
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and not in legacy boot
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@retval None
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**/
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VOID
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EFIAPI
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PchUpdateNvsOnExitBootServices (
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VOID
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);
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#endif // _PCH_INITIALIZATION_DRIVER_H_
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