/** @file
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This is the Common driver that initializes the Intel PCH.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PchInit.h"
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//
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// Module variables
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//
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GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *mPchConfigHob;
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GLOBAL_REMOVE_IF_UNREFERENCED SI_CONFIG_HOB *mSiConfigHob;
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/**
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Common PchInit Module Entry Point
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**/
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VOID
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PchInitEntryPointCommon (
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VOID
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)
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{
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EFI_PEI_HOB_POINTERS HobPtr;
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DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() Start\n"));
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//
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// Get PCH Config HOB.
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//
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HobPtr.Guid = GetFirstGuidHob (&gPchConfigHobGuid);
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ASSERT (HobPtr.Guid != NULL);
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mPchConfigHob = (PCH_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid);
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//
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// Get Silicon Config data HOB
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//
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HobPtr.Guid = GetFirstGuidHob (&gSiConfigHobGuid);
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ASSERT (HobPtr.Guid != NULL);
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mSiConfigHob = (SI_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid);
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DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() End\n"));
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return;
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}
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/**
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Lock USB registers before boot
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@param[in] PchConfigHob The PCH Config HOB
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**/
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VOID
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LockXhciConfiguration (
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IN CONST PCH_CONFIG_HOB *PchConfigHob
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)
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{
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UINTN XhciPciMmBase;
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UINT32 XhccCfg;
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DEBUG ((DEBUG_INFO, "LockXhciConfiguration () - Start\n"));
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XhciPciMmBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_XHCI,
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PCI_FUNCTION_NUMBER_PCH_XHCI
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);
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///
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/// PCH BIOS Spec Section 13.2.4 Locking xHCI Register Settings
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/// PCH BIOS Spec Locking xHCI Register settings
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/// After xHCI is initialized, BIOS should lock the xHCI configuration registers to RO.
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/// This prevent any unintended changes. There is also a lockdown feature for OverCurrent
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/// registers. BIOS should set these bits to lock down the settings prior to end of POST.
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/// 1. Set Access Control bit at XHCI PCI offset 40h[31] to 1b to lock xHCI register settings.
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/// 2. Set OC Configuration Done bit at XHCI PCI offset 44h[31] to lock overcurrent mappings from
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/// further changes.
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///
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MmioOr32 (XhciPciMmBase + R_PCH_XHCI_XHCC2, (UINT32) (BIT31));
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (XhciPciMmBase + R_PCH_XHCI_XHCC2),
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1,
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(VOID *) (UINTN) (XhciPciMmBase + R_PCH_XHCI_XHCC2)
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);
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///
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/// PCH BIOS Spec xHCI controller setup
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/// Note:
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/// XHCI PCI offset 40h is write once register.
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/// Unsupported Request Detected bit is write clear
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///
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XhccCfg = MmioRead32 (XhciPciMmBase + R_PCH_XHCI_XHCC1);
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XhccCfg &= (UINT32) ~(B_PCH_XHCI_XHCC1_URD);
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XhccCfg |= (UINT32) (B_PCH_XHCI_XHCC1_ACCTRL);
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MmioWrite32 (XhciPciMmBase + R_PCH_XHCI_XHCC1, XhccCfg);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (XhciPciMmBase + R_PCH_XHCI_XHCC1),
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1,
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(VOID *) (UINTN) (XhciPciMmBase + R_PCH_XHCI_XHCC1)
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);
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DEBUG ((DEBUG_INFO, "LockXhciConfiguration () - End\n"));
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}
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/**
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Process all the lock downs
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**/
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VOID
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ProcessAllLocks (
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VOID
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)
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{
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UINTN Index;
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UINT8 Data8;
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UINT16 Data16And;
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UINT16 Data16Or;
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UINT32 Data32;
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UINT32 Data32And;
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UINT32 Data32Or;
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UINT32 DlockValue;
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UINTN PciLpcRegBase;
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UINTN PciSpiRegBase;
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UINTN PciPmcRegBase;
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UINT16 TcoBase;
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UINT32 PchPwrmBase;
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UINTN PchSpiBar0;
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PciLpcRegBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_LPC,
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PCI_FUNCTION_NUMBER_PCH_LPC
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);
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PciPmcRegBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_PMC,
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PCI_FUNCTION_NUMBER_PCH_PMC
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);
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PciSpiRegBase = MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI
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);
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PchSpiBar0 = MmioRead32 (PciSpiRegBase + R_PCH_SPI_BAR0) &~(B_PCH_SPI_BAR0_MASK);
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PchTcoBaseGet (&TcoBase);
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//
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// Lock XHCI configuration
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//
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LockXhciConfiguration (mPchConfigHob);
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///
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/// Set PWRMBASE + 620h [31] to lock the ST and NST PG register fields.
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///
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ConfigurePmcStaticFunctionDisableLock ();
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///
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/// SKL PCH BWG 7.2.4 Additional PCH DMI and OP-DMI Programming Steps
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/// Step 9.2
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/// Set PCR[DMI] + 2234h [31] = 1b.
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/// Leave this in DXE since setting it in PEI would break the ActiveBIOS module.
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///
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Data32And = 0xFFFFFFFF;
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Data32Or = B_PCH_PCR_DMI_DMIC_SRL;
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PchPcrAndThenOr32 (
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PID_DMI, R_PCH_PCR_DMI_DMIC,
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Data32And,
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Data32Or
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);
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PCH_PCR_BOOT_SCRIPT_READ_WRITE (
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S3BootScriptWidthUint32,
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PID_DMI, R_PCH_PCR_DMI_DMIC,
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&Data32Or,
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&Data32And
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);
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///
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/// Program the Flash Protection Range Register based on policy
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///
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DlockValue = MmioRead32 (PchSpiBar0 + R_PCH_SPI_DLOCK);
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for (Index = 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) {
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if ((mPchConfigHob->ProtectRange[Index].WriteProtectionEnable ||
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mPchConfigHob->ProtectRange[Index].ReadProtectionEnable) != TRUE) {
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continue;
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}
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///
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/// Proceed to program the register after ensure it is enabled
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///
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Data32 = 0;
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Data32 |= (mPchConfigHob->ProtectRange[Index].WriteProtectionEnable == TRUE) ? B_PCH_SPI_PRX_WPE : 0;
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Data32 |= (mPchConfigHob->ProtectRange[Index].ReadProtectionEnable == TRUE) ? B_PCH_SPI_PRX_RPE : 0;
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Data32 |= ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRangeLimit << N_PCH_SPI_PRX_PRL) & B_PCH_SPI_PRX_PRL_MASK;
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Data32 |= ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRangeBase << N_PCH_SPI_PRX_PRB) & B_PCH_SPI_PRX_PRB_MASK;
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DEBUG ((DEBUG_INFO, "Protected range %d: 0x%08x \n", Index, Data32));
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DlockValue |= (UINT32) (B_PCH_SPI_DLOCK_PR0LOCKDN << Index);
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MmioWrite32 ((UINTN) (PchSpiBar0 + (R_PCH_SPI_PR0 + (Index * S_PCH_SPI_PRX))), Data32);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + (R_PCH_SPI_PR0 + (Index * S_PCH_SPI_PRX))),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + (R_PCH_SPI_PR0 + (Index * S_PCH_SPI_PRX)))
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);
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}
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//
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// Program DLOCK register
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//
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MmioWrite32 ((UINTN) (PchSpiBar0 + R_PCH_SPI_DLOCK), DlockValue);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_PCH_SPI_DLOCK),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_PCH_SPI_DLOCK)
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);
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// In PCH SPI controller the BIOS should set the Flash Configuration Lock-Down bit
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/// (SPI_BAR0 + 04[15]) at end of post. When set to 1, those Flash Program Registers
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/// that are locked down by this FLOCKDN bit cannot be written.
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/// Please refer to the EDS for which program registers are impacted.
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///
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MmioOr32 ((UINTN) (PchSpiBar0 + R_PCH_SPI_HSFSC), (UINT32) (B_PCH_SPI_HSFSC_FLOCKDN));
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_PCH_SPI_HSFSC),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_PCH_SPI_HSFSC)
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);
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///
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/// SPI Flash Programming Guide Section 5.5.2 Vendor Component Lock
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/// It is strongly recommended that BIOS sets the Vendor Component Lock (VCL) bits. VCL applies
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/// the lock to both VSCC0 and VSCC1 even if VSCC0 is not used. Without the VCL bits set, it is
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/// possible to make Host/GbE VSCC register(s) changes in that can cause undesired host and
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/// integrated GbE Serial Flash functionality.
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///
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MmioOr32 ((UINTN) (PchSpiBar0 + R_PCH_SPI_SFDP0_VSCC0), B_PCH_SPI_SFDP0_VSCC0_VCL);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint32,
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(UINTN) (PchSpiBar0 + R_PCH_SPI_SFDP0_VSCC0),
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1,
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(VOID *) (UINTN) (PchSpiBar0 + R_PCH_SPI_SFDP0_VSCC0)
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);
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///
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/// Additional Power Management Programming
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/// Step 3
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/// Set GEN_PMCON_LOCK register, PMC PCI offset A6h = 06h, after stretch and ACPI base programming completed.
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///
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MmioOr8 (
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(UINTN) (PciPmcRegBase + R_PCH_PMC_GEN_PMCON_B + 2),
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(UINT8) ((B_PCH_PMC_GEN_PMCON_B_SLPSX_STR_POL_LOCK | B_PCH_PMC_GEN_PMCON_B_ACPI_BASE_LOCK) >> 16)
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);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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(UINTN) (PciPmcRegBase + R_PCH_PMC_GEN_PMCON_B + 2),
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1,
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(VOID *) (UINTN) (PciPmcRegBase + R_PCH_PMC_GEN_PMCON_B + 2)
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);
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// BIOS needs to enable the BIOS Lock Enable (BLE) feature of the PCH by setting
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/// SPI/eSPI/LPC PCI offset DCh[1] = 1b.
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/// When this bit is set, attempts to write the BIOS Write Enable (BIOSWE) bit
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/// in PCH will cause a SMI which will allow the BIOS to verify that the write is
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/// from a valid source.
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/// Remember that BIOS needs to set SPI/LPC/eSPI PCI Offset DC [0] = 0b to enable
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/// BIOS region protection before exiting the SMI handler.
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/// Also, TCO_EN bit needs to be set (SMI_EN Register, ABASE + 30h[13] = 1b) to keep
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/// BLE feature enabled after booting to the OS.
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/// Intel requires that BIOS enables the Lock Enable (LE) feature of the PCH to
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/// ensure SMM protection of flash.
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/// Left to platform code to register a callback function to handle BiosWp SMI
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///
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if (mPchConfigHob->LockDown.BiosLock == TRUE) {
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//
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// eSPI/LPC
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//
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if (! (MmioRead8 (PciLpcRegBase + R_PCH_LPC_BC) & B_PCH_LPC_BC_LE)) {
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DEBUG ((DEBUG_INFO, "Set LPC bios lock\n"));
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MmioOr8 ((UINTN) (PciLpcRegBase + R_PCH_LPC_BC), B_PCH_LPC_BC_LE);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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(UINTN) (PciLpcRegBase + R_PCH_LPC_BC),
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1,
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(VOID *) (UINTN) (PciLpcRegBase + R_PCH_LPC_BC)
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);
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}
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//
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// SPI
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//
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if (! (MmioRead8 (PciSpiRegBase + R_PCH_SPI_BC) & B_PCH_SPI_BC_LE)) {
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DEBUG ((DEBUG_INFO, "Set SPI bios lock\n"));
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MmioOr8 ((UINTN) (PciSpiRegBase + R_PCH_SPI_BC), (UINT8) B_PCH_SPI_BC_LE);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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(UINTN) (PciSpiRegBase + R_PCH_SPI_BC),
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1,
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(VOID *) (UINTN) (PciSpiRegBase + R_PCH_SPI_BC)
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);
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}
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}
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///
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/// PCH BIOS Spec Section 3.6 Flash Security Recommendation
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/// BIOS also needs to set the BIOS Interface Lock Down bit in multiple locations
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/// (PCR[DMI] + 274Ch[0], LPC/eSPI PCI offset DCh[7] and SPI PCI offset DCh[7]).
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/// Setting these bits will prevent writes to the Top Swap bit (under their respective locations)
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/// and the Boot BIOS Straps. Enabling this bit will mitigate malicious software
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/// attempts to replace the system BIOS option ROM with its own code.
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///
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if (mPchConfigHob->LockDown.BiosInterface == TRUE) {
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///
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/// LPC
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///
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MmioOr8 ((UINTN) (PciLpcRegBase + R_PCH_LPC_BC), (UINT32) B_PCH_LPC_BC_BILD);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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(UINTN) (PciLpcRegBase + R_PCH_LPC_BC),
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1,
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(VOID *) (UINTN) (PciLpcRegBase + R_PCH_LPC_BC)
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);
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///
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/// Reads back for posted write to take effect
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///
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Data8 = MmioRead8 ((UINTN) (PciLpcRegBase + R_PCH_LPC_BC));
|
S3BootScriptSaveMemPoll (
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S3BootScriptWidthUint8,
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(UINTN) (PciLpcRegBase + R_PCH_LPC_BC),
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&Data8, // BitMask
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&Data8, // BitValue
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1, // Duration
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1 // LoopTimes
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);
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///
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/// SPI
|
///
|
MmioOr8 ((UINTN) (PciSpiRegBase + R_PCH_SPI_BC), (UINT32) B_PCH_SPI_BC_BILD);
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S3BootScriptSaveMemWrite (
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S3BootScriptWidthUint8,
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(UINTN) (PciSpiRegBase + R_PCH_SPI_BC),
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1,
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(VOID *) (UINTN) (PciSpiRegBase + R_PCH_SPI_BC)
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);
|
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///
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/// Reads back for posted write to take effect
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///
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Data8 = MmioRead8 ((UINTN) (PciSpiRegBase + R_PCH_SPI_BC));
|
S3BootScriptSaveMemPoll (
|
S3BootScriptWidthUint8,
|
(UINTN) (PciSpiRegBase + R_PCH_SPI_BC),
|
&Data8, // BitMask
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&Data8, // BitValue
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1, // Duration
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1 // LoopTimes
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);
|
|
///
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/// Set PCR[DMI] + 274C[0] = 1b
|
///
|
Data32And = 0xFFFFFFFF;
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Data32Or = B_PCH_PCR_DMI_BILD;
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PchPcrAndThenOr32 (PID_DMI, R_PCH_PCR_DMI_GCS, Data32And, Data32Or);
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PCH_PCR_BOOT_SCRIPT_READ_WRITE (
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S3BootScriptWidthUint32,
|
PID_DMI, R_PCH_PCR_DMI_GCS,
|
&Data32Or,
|
&Data32And
|
);
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}
|
|
///
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/// PCH BIOS Spec Section 5.13 BIOS guide on using RTC RAM
|
/// For Data integrity protection, set RTC Memory locks (Upper 128 Byte Lock and
|
/// Lower 128 Byte Lock) at SBCR[RTC] + 3400h[4] and SBCR[RTC] + 3400h[3]. Note once locked
|
/// bytes 0x38 - 0x3F in each of the Upper and Lower Byte blocks, respectively,
|
/// cannot be unlocked until next reset.
|
///
|
if (mPchConfigHob->LockDown.RtcLock == TRUE) {
|
Data32And = 0xFFFFFFFF;
|
Data32Or = (B_PCH_PCR_RTC_CONF_UCMOS_LOCK | B_PCH_PCR_RTC_CONF_LCMOS_LOCK | B_PCH_PCR_RTC_CONF_RESERVED);
|
PchPcrAndThenOr32 (
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PID_RTC, R_PCH_PCR_RTC_CONF,
|
Data32And,
|
Data32Or
|
);
|
PCH_PCR_BOOT_SCRIPT_READ_WRITE (
|
S3BootScriptWidthUint32,
|
PID_RTC, R_PCH_PCR_RTC_CONF,
|
&Data32Or,
|
&Data32And
|
);
|
}
|
|
///
|
/// Lock Down TCO
|
///
|
Data16And = 0xFFFF;
|
Data16Or = B_PCH_TCO_CNT_LOCK;
|
IoOr16 (TcoBase + R_PCH_TCO1_CNT, Data16Or);
|
S3BootScriptSaveIoReadWrite (
|
S3BootScriptWidthUint16,
|
(UINTN) (TcoBase + R_PCH_TCO1_CNT),
|
&Data16Or, // Data to be ORed
|
&Data16And // Data to be ANDed
|
);
|
|
///
|
/// PCH BIOS Spec Section 5.15.1 Additional Chipset Initialization
|
/// Step 1
|
/// Set SPIBAR0 + F0h [0] to 1b
|
///
|
MmioOr8 ((UINTN) (PchSpiBar0 + R_PCH_SPI_SSML), B_PCH_SPI_SSML_SSL);
|
|
//
|
// Lock Down PMC
|
// Set PWRM + 0x18 [27, 22] prior to OS.
|
//
|
PchPwrmBaseGet (&PchPwrmBase);
|
Data32Or = BIT27;
|
if (mPchConfigHob->Pm.PmcReadDisable) {
|
Data32Or |= BIT22;
|
}
|
MmioOr32 (PchPwrmBase + R_PCH_PWRM_CFG, Data32Or);
|
S3BootScriptSaveMemWrite (
|
S3BootScriptWidthUint32,
|
(UINTN) (PchPwrmBase + R_PCH_PWRM_CFG),
|
1,
|
(VOID *) (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG)
|
);
|
}
|
|
/**
|
Set eSPI BME bit
|
**/
|
VOID
|
ConfigureEspiBme (
|
VOID
|
)
|
{
|
}
|
|
/**
|
Common PCH initialization before Boot Sript Table is closed
|
|
**/
|
VOID
|
PchOnPciEnumCompleteCommon (
|
VOID
|
)
|
{
|
UINT32 Data32Or;
|
UINT32 Data32And;
|
|
DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteCommon() Start\n"));
|
|
ProcessAllLocks ();
|
|
///
|
/// Perform remaining configuration for PCH SATA on End of DXE
|
///
|
ConfigurePchSataOnEndOfDxe ();
|
|
///
|
/// PSTHCTL (0xD00h[2]) = 1, PSTH IOSF Primary Trunk Clock Gating Enable (PSTHIOSFPTCGE)
|
///
|
Data32And = 0xFFFFFFFF;
|
Data32Or = B_PCH_PCR_PSTH_PSTHIOSFPTCGE;
|
PchPcrAndThenOr32 (PID_PSTH, R_PCH_PCR_PSTH_PSTHCTL, Data32And, Data32Or);
|
PCH_PCR_BOOT_SCRIPT_READ_WRITE (
|
S3BootScriptWidthUint32,
|
PID_PSTH, R_PCH_PCR_PSTH_PSTHCTL,
|
&Data32Or,
|
&Data32And
|
);
|
|
//
|
// Set eSPI BME after PCI enumeration
|
//
|
ConfigureEspiBme ();
|
|
//
|
// This function process P2SB configuration
|
// This MUST be executed in very end of End Of Dxe
|
// All PSF access after this function will not acceptable
|
//
|
ConfigureP2sbSbiLock ((BOOLEAN) mPchConfigHob->P2sb.SbiUnlock);
|
|
DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteCommon() End\n"));
|
}
|
