/** @file
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Routines for Rst remapping
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Library/RstPrivateLib.h>
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#include <PchPcieStorageDetectHob.h>
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/**
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Checks whether device on given Root Port is remap capable
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@param[in] RpNumber Root Port Number
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@param[in] TempPciBus Temporary Pci Bus
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@retval UINT8 Device Programming Interface
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**/
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UINT8
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RstGetProgInterfaceForRemapDevice (
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IN UINT32 RpNumber,
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IN UINT32 TempPciBus
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)
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{
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UINTN RpDevice;
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UINTN RpFunction;
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UINT8 BusNumber;
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UINTN EpBase;
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UINT8 PiInterface;
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UINTN RpBase;
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UINT8 ClassCode;
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UINT8 SubClassCode;
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DEBUG ((DEBUG_INFO, "Detect storage device on Rp: %d\n", RpNumber));
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GetPchPcieRpDevFun (RpNumber, &RpDevice, &RpFunction);
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BusNumber = DEFAULT_PCI_BUS_NUMBER_PCH;
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PiInterface = RST_PCIE_STORAGE_INTERFACE_NONE;
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RpBase = MmPciBase (BusNumber, (UINT32) RpDevice, (UINT32) RpFunction);
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if (MmioRead16 (RpBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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DEBUG((DEBUG_INFO, "RstGetProgInterfaceForRemapDevices: RootPort does not exists Rp = %d\n", RpNumber));
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return PiInterface;
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}
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//
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// Assign Temporary Bus Number
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//
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MmioAndThenOr32 (
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RpBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET,
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(UINT32) ~B_PCI_BRIDGE_BNUM_SBBN_SCBN,
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((UINT32) (TempPciBus << 8)) | ((UINT32) (TempPciBus << 16))
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);
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//
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// A config write is required in order for the device to re-capture the Bus number,
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// according to PCI Express Base Specification, 2.2.6.2
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// Write to a read-only register VendorID to not cause any side effects.
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//
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EpBase = MmPciBase (TempPciBus, 0, 0);
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MmioWrite16 (EpBase + PCI_VENDOR_ID_OFFSET, 0);
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//
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// Read Vendor Id to check if device exists
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// if not clear bus number and return RST_PCIE_STORAGE_INTERFACE_NONE
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//
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if (MmioRead16 (EpBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
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MmioAnd32 (RpBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, (UINT32) ~B_PCI_BRIDGE_BNUM_SBBN_SCBN);
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return PiInterface;
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}
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ClassCode = MmioRead8 (EpBase + R_PCI_BCC_OFFSET);
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SubClassCode = MmioRead8 (EpBase + R_PCI_SCC_OFFSET);
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PiInterface = MmioRead8 (EpBase + R_PCI_PI_OFFSET);
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if ( ClassCode == PCI_CLASS_MASS_STORAGE) {
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DEBUG ((DEBUG_INFO, "RstGetProgInterfaceForRemapDevice: ClassCode = %X, SubClassCode = %X, PiInterface = %X\n", ClassCode, SubClassCode, PiInterface));
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if (SubClassCode == PCI_CLASS_MASS_STORAGE_AHCI) {
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if (PiInterface == RST_PCIE_STORAGE_INTERFACE_AHCI) {
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DEBUG ((DEBUG_INFO, "RstGetProgInterfaceForRemapDevice: AHCI Card found on Rp: %d\n", RpNumber));
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}
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} else if (SubClassCode == PCI_CLASS_MASS_STORAGE_NVME) {
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if (PiInterface == RST_PCIE_STORAGE_INTERFACE_NVME) {
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DEBUG ((DEBUG_INFO, "RstGetProgInterfaceForRemapDevice: NVMe Card found on Rp: %d\n", RpNumber));
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}
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} else if (SubClassCode == PCI_CLASS_MASS_STORAGE_RAID) {
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DEBUG ((DEBUG_INFO, "RstGetProgInterfaceForRemapDevice: RAID Card found on Rp: %d\n", RpNumber));
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PiInterface = RST_PCIE_STORAGE_INTERFACE_NVME;
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}
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}
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//
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// Clear temporary bus number
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//
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MmioAnd32 (RpBase + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, (UINT32) ~B_PCI_BRIDGE_BNUM_SBBN_SCBN);
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return PiInterface;
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}
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/**
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Check the lane occupied by certain root port according to the root port number and configuration strap
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Return 8-bit bitmap where each bit represents the lane number (e.g.: return 00000011b means the root port owns 2 lane)
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@param[in] RootPortNum Root Port Number
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@retval UINT8 Lane Occupied by the Root Port (bitmap)
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**/
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UINT8
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RstGetRpLaneOccupyMask (
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IN UINT32 RootPortNum
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)
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{
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EFI_STATUS Status;
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UINT32 CtrlNum;
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UINT32 CtrlFirstRpNum;
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UINT32 Data32;
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UINT8 LaneOccupied;
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LaneOccupied = 0;
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CtrlNum = RootPortNum / PCH_PCIE_CONTROLLER_PORTS;
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CtrlFirstRpNum = CtrlNum * PCH_PCIE_CONTROLLER_PORTS;
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//
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// Read the Root Port Configuration Straps for the link width, and return LaneOccupied by the Root Port accordingly
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//
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Status = PchSbiRpPciRead32 (CtrlFirstRpNum, R_PCH_PCIE_STRPFUSECFG, &Data32);
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ASSERT_EFI_ERROR (Status);
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switch ((Data32 & B_PCH_PCIE_STRPFUSECFG_RPC) >> N_PCH_PCIE_STRPFUSECFG_RPC) {
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case V_PCH_PCIE_STRPFUSECFG_RPC_4:
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if (RootPortNum % 4 == 0) {
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LaneOccupied = (BIT3|BIT2|BIT1|BIT0);
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}
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break;
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case V_PCH_PCIE_STRPFUSECFG_RPC_2_2:
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if ((RootPortNum % 2 == 0)) {
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LaneOccupied = (BIT1|BIT0);
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}
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break;
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case V_PCH_PCIE_STRPFUSECFG_RPC_2_1_1:
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if (RootPortNum % 4 == 0) {
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LaneOccupied = (BIT1|BIT0);
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} else if (RootPortNum % 4 != 1) {
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LaneOccupied = BIT0;
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}
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break;
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case V_PCH_PCIE_STRPFUSECFG_RPC_1_1_1_1:
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LaneOccupied = BIT0;
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break;
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default:
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break;
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}
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return LaneOccupied;
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}
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/**
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Checks PCH generation and returns SATA's GCR.PLS bit number according to root port number with a PCIe storage device
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connected to.
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@param[in] RootPortNum Root port number which PCIe storage device is connected to
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@retval UINT32 Number of GCR.PLS bit representing root port
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**/
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UINT32
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RstPlsBitNumber (
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IN UINT32 RootPortNum
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)
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{
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if ((GetPchGeneration () == KblPch) && (RstGetCycleRouterNumber (RootPortNum) == RST_PCIE_STORAGE_CR_2)) {
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return RootPortNum - 2 * PCH_PCIE_CONTROLLER_PORTS;
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} else {
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return RootPortNum;
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}
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}
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/**
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Checks if device with given PCI config space address is Intel's Stony Beach.
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@param[in] EndPointPciBase Address of device's PCI config space
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@retval BOOLEAN TRUE if device is Intel's Stony Beach, FALSE othrwise
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**/
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BOOLEAN
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RstIsStonyBeach (
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IN UINTN EndPointPciBase
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)
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{
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UINT16 DeviceVendorId;
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UINT16 DeviceDeviceId;
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DeviceVendorId = MmioRead16 (EndPointPciBase + PCI_VENDOR_ID_OFFSET);
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DeviceDeviceId = MmioRead16 (EndPointPciBase + PCI_DEVICE_ID_OFFSET);
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if (DeviceVendorId == RST_STONY_BEACH_VENDOR_ID && DeviceDeviceId == RST_STONY_BEACH_DEVICE_ID) {
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return TRUE;
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}
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return FALSE;
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}
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