/** @file
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PCH Smbus Executive Code (common PEI/DXE/SMM code)
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/TimerLib.h>
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#include <IndustryStandard/SmBus.h>
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#include <IndustryStandard/Pci30.h>
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#include <PchAccess.h>
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#include <Library/MmPciLib.h>
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#include <Library/PchSmbusCommonLib.h>
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/**
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Get SMBUS IO Base address
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|
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@retval UINT32 The SMBUS IO Base Address
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**/
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UINT32
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SmbusGetIoBase (
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VOID
|
)
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{
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UINT32 SmbusIoBase;
|
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SmbusIoBase = MmioRead32 (
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MmPciBase (
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DEFAULT_PCI_BUS_NUMBER_PCH,
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PCI_DEVICE_NUMBER_PCH_SMBUS,
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PCI_FUNCTION_NUMBER_PCH_SMBUS)
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+ R_PCH_SMBUS_BASE) & B_PCH_SMBUS_BASE_BAR;
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ASSERT (SmbusIoBase != B_PCH_SMBUS_BASE_BAR && SmbusIoBase != 0);
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return SmbusIoBase;
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}
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/**
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This function provides a standard way to read PCH Smbus IO registers.
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@param[in] Offset Register offset from Smbus base IO address.
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@retval UINT8 Returns data read from IO.
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**/
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UINT8
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EFIAPI
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SmbusIoRead (
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IN UINT8 Offset
|
)
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{
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return IoRead8 (SmbusGetIoBase () + Offset);
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}
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/**
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This function provides a standard way to write PCH Smbus IO registers.
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@param[in] Offset Register offset from Smbus base IO address.
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@param[in] Data Data to write to register.
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**/
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VOID
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EFIAPI
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SmbusIoWrite (
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IN UINT8 Offset,
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IN UINT8 Data
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)
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{
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///
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/// Write New Value
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///
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IoWrite8 (SmbusGetIoBase () + Offset, Data);
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return;
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}
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/**
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This function provides a standard way to check if an SMBus transaction has
|
completed.
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@param[in] StsReg Not used for input. On return, contains the
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value of the SMBus status register.
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@retval TRUE Transaction is complete
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@retval FALSE Otherwise.
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**/
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BOOLEAN
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EFIAPI
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IoDone (
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IN UINT8 *StsReg
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)
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{
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///
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/// Wait for IO to complete
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///
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UINTN StallIndex;
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UINTN StallTries;
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StallTries = STALL_TIME / STALL_PERIOD;
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for (StallIndex = 0; StallIndex < StallTries; StallIndex++) {
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*StsReg = SmbusIoRead (R_PCH_SMBUS_HSTS);
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if (*StsReg & (B_PCH_SMBUS_INTR | B_PCH_SMBUS_BYTE_DONE_STS | B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR)) {
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return TRUE;
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} else {
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MicroSecondDelay (STALL_PERIOD);
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}
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}
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return FALSE;
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}
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/**
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Check if it's ok to use the bus.
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@retval EFI_SUCCESS SmBus is acquired and it's safe to send commands.
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@retval EFI_TIMEOUT SmBus is busy, it's not safe to send commands.
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**/
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EFI_STATUS
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AcquireBus (
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VOID
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)
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{
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UINT8 StsReg;
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StsReg = 0;
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StsReg = SmbusIoRead (R_PCH_SMBUS_HSTS);
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if (StsReg & B_PCH_SMBUS_IUS) {
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return EFI_TIMEOUT;
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} else if (StsReg & B_PCH_SMBUS_HBSY) {
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///
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/// Clear Status Register and exit
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///
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SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
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return EFI_TIMEOUT;
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} else {
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///
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/// Clear out any odd status information (Will Not Clear In Use)
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///
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SmbusIoWrite (R_PCH_SMBUS_HSTS, StsReg);
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return EFI_SUCCESS;
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}
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}
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/**
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This function provides a standard way to execute Smbus protocols
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as defined in the SMBus Specification. The data can either be of
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the Length byte, word, or a block of data. The resulting transaction will be
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either the SMBus Slave Device accepts this transaction or this function
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returns with an error
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@param[in] SlaveAddress Smbus Slave device the command is directed at
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@param[in] Command Slave Device dependent
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@param[in] Operation Which SMBus protocol will be used
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@param[in] PecCheck Defines if Packet Error Code Checking is to be used
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@param[in, out] Length How many bytes to read. Must be 0 <= Length <= 32 depending on Operation
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It will contain the actual number of bytes read/written.
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@param[in, out] Buffer Contain the data read/written.
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@retval EFI_SUCCESS The operation completed successfully.
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@exception EFI_UNSUPPORTED The operation is unsupported.
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@retval EFI_INVALID_PARAMETER Length or Buffer is NULL for any operation besides
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quick read or quick write.
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@retval EFI_TIMEOUT The transaction did not complete within an internally
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specified timeout period, or the controller is not
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available for use.
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@retval EFI_DEVICE_ERROR There was an Smbus error (NACK) during the operation.
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This could indicate the slave device is not present
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or is in a hung condition.
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**/
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EFI_STATUS
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SmbusExec (
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IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress,
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IN EFI_SMBUS_DEVICE_COMMAND Command,
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IN EFI_SMBUS_OPERATION Operation,
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IN BOOLEAN PecCheck,
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IN OUT UINTN *Length,
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IN OUT VOID *Buffer
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)
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{
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EFI_STATUS Status;
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UINT8 AuxcReg;
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UINT8 AuxStsReg;
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UINT8 SmbusOperation;
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UINT8 StsReg;
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UINT8 SlvAddrReg;
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UINT8 HostCmdReg;
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UINT8 BlockCount;
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BOOLEAN BufferTooSmall;
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UINTN Index;
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UINTN BusIndex;
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UINT8 *CallBuffer;
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UINT8 SmbusHctl;
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UINT32 Timeout;
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CallBuffer = Buffer;
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BlockCount = 0;
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///
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/// For any operations besides quick read & write, the pointers to
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/// Length and Buffer must not be NULL.
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///
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if ((Operation != EfiSmbusQuickRead) && (Operation != EfiSmbusQuickWrite)) {
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if ((Length == NULL) || (Buffer == NULL)) {
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return EFI_INVALID_PARAMETER;
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}
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}
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///
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/// See if its ok to use the bus based upon INUSE_STS bit.
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///
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Status = AcquireBus ();
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if (EFI_ERROR (Status)) {
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return Status;
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}
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///
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/// This is the main operation loop. If the operation results in a Smbus
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/// collision with another master on the bus, it attempts the requested
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/// transaction again at least BUS_TRIES attempts.
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///
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for (BusIndex = 0; BusIndex < BUS_TRIES; BusIndex++) {
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///
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/// Operation Specifics (pre-execution)
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///
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Status = EFI_SUCCESS;
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_QUICK;
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SlvAddrReg = (UINT8) ((SlaveAddress.SmbusDeviceAddress << 1) | 1);
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HostCmdReg = (UINT8) Command;
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AuxcReg = 0;
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switch (Operation) {
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case EfiSmbusQuickWrite:
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SlvAddrReg--;
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///
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/// The "break;" command is not present here to allow code execution
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/// do drop into the next case, which contains common code to this case.
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///
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case EfiSmbusQuickRead:
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if (PecCheck == TRUE) {
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Status = EFI_UNSUPPORTED;
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}
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break;
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case EfiSmbusSendByte:
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HostCmdReg = CallBuffer[0];
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SlvAddrReg--;
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///
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/// The "break;" command is not present here to allow code execution
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/// do drop into the next case, which contains common code to this case.
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///
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case EfiSmbusReceiveByte:
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE;
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if (*Length < 1) {
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Status = EFI_BUFFER_TOO_SMALL;
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}
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*Length = 1;
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break;
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case EfiSmbusWriteByte:
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SmbusIoWrite (R_PCH_SMBUS_HD0, CallBuffer[0]);
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SlvAddrReg--;
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*Length = 1;
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///
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/// The "break;" command is not present here to allow code execution
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/// do drop into the next case, which contains common code to this case.
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///
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case EfiSmbusReadByte:
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if (*Length < 1) {
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Status = EFI_BUFFER_TOO_SMALL;
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} else if (*Length == 1) {
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_BYTE_DATA;
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} else if (*Length <= 256) {
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if (PecCheck == TRUE) {
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///
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/// The I2C Read command with either PEC_EN or AAC bit set
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/// produces undefined results.
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///
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Status = EFI_UNSUPPORTED;
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}
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_IIC_READ;
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} else {
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Status = EFI_INVALID_PARAMETER;
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}
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break;
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case EfiSmbusReadWord:
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_WORD_DATA;
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if (*Length < 2) {
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Status = EFI_BUFFER_TOO_SMALL;
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}
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*Length = 2;
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break;
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case EfiSmbusWriteWord:
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_WORD_DATA;
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SlvAddrReg--;
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SmbusIoWrite (R_PCH_SMBUS_HD1, CallBuffer[1]);
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SmbusIoWrite (R_PCH_SMBUS_HD0, CallBuffer[0]);
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if (*Length < 2) {
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Status = EFI_BUFFER_TOO_SMALL;
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}
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*Length = 2;
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break;
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case EfiSmbusWriteBlock:
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SmbusIoWrite (R_PCH_SMBUS_HD0, *(UINT8 *) Length);
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SlvAddrReg--;
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BlockCount = (UINT8) (*Length);
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///
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/// The "break;" command is not present here to allow code execution
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/// do drop into the next case, which contains common code to this case.
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///
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case EfiSmbusReadBlock:
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK;
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if ((*Length < 1) || (*Length > 32)) {
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Status = EFI_INVALID_PARAMETER;
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break;
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}
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AuxcReg |= B_PCH_SMBUS_E32B;
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break;
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case EfiSmbusProcessCall:
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_PROCESS_CALL;
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SmbusIoWrite (R_PCH_SMBUS_HD1, CallBuffer[1]);
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SmbusIoWrite (R_PCH_SMBUS_HD0, CallBuffer[0]);
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if (*Length < 2) {
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Status = EFI_BUFFER_TOO_SMALL;
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}
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*Length = 2;
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break;
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case EfiSmbusBWBRProcessCall:
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///
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/// The write byte count cannot be zero or more than
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/// 32 bytes.
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///
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if ((*Length < 1) || (*Length > 32)) {
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Status = EFI_INVALID_PARAMETER;
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break;
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}
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SmbusIoWrite (R_PCH_SMBUS_HD0, *(UINT8 *) Length);
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BlockCount = (UINT8) (*Length);
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SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK_PROCESS;
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AuxcReg |= B_PCH_SMBUS_E32B;
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break;
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default:
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Status = EFI_INVALID_PARAMETER;
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break;
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}
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if (EFI_ERROR (Status)) {
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break;
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}
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if (PecCheck == TRUE) {
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AuxcReg |= B_PCH_SMBUS_AAC;
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}
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///
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/// Set Auxiliary Control register
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///
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SmbusIoWrite (R_PCH_SMBUS_AUXC, AuxcReg);
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///
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/// Reset the pointer of the internal buffer
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///
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SmbusIoRead (R_PCH_SMBUS_HCTL);
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///
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/// Now that the 32 byte buffer is turned on, we can write th block data
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/// into it
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///
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if ((Operation == EfiSmbusWriteBlock) || (Operation == EfiSmbusBWBRProcessCall)) {
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for (Index = 0; Index < BlockCount; Index++) {
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///
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/// Write next byte
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///
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SmbusIoWrite (R_PCH_SMBUS_HBD, CallBuffer[Index]);
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}
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}
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///
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/// Set SMBus slave address for the device to send/receive from
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///
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SmbusIoWrite (R_PCH_SMBUS_TSA, SlvAddrReg);
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///
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/// For I2C read, send DATA1 register for the offset (address)
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/// within the serial memory chips
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///
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if ((Operation == EfiSmbusReadByte) && (*Length > 1)) {
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SmbusIoWrite (R_PCH_SMBUS_HD1, HostCmdReg);
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} else {
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///
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/// Set Command register
|
///
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SmbusIoWrite (R_PCH_SMBUS_HCMD, HostCmdReg);
|
}
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///
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/// Set Control Register (Initiate Operation, Interrupt disabled)
|
///
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SmbusIoWrite (R_PCH_SMBUS_HCTL, (UINT8) (SmbusOperation + B_PCH_SMBUS_START));
|
|
///
|
/// Wait for IO to complete
|
///
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if (!IoDone (&StsReg)) {
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Status = EFI_TIMEOUT;
|
break;
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} else if (StsReg & B_PCH_SMBUS_DERR) {
|
AuxStsReg = SmbusIoRead (R_PCH_SMBUS_AUXS);
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if (AuxStsReg & B_PCH_SMBUS_CRCE) {
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Status = EFI_CRC_ERROR;
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} else {
|
Status = EFI_DEVICE_ERROR;
|
}
|
break;
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} else if (StsReg & B_PCH_SMBUS_BERR) {
|
///
|
/// Clear the Bus Error for another try
|
///
|
Status = EFI_DEVICE_ERROR;
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SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);
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///
|
/// Clear Status Registers
|
///
|
SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
|
SmbusIoWrite (R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
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///
|
/// If bus collision happens, stall some time, then try again
|
/// Here we choose 10 milliseconds to avoid MTCP transfer.
|
///
|
MicroSecondDelay (STALL_PERIOD);
|
continue;
|
}
|
///
|
/// successfull completion
|
/// Operation Specifics (post-execution)
|
///
|
switch (Operation) {
|
|
case EfiSmbusReadWord:
|
///
|
/// The "break;" command is not present here to allow code execution
|
/// do drop into the next case, which contains common code to this case.
|
///
|
case EfiSmbusProcessCall:
|
CallBuffer[1] = SmbusIoRead (R_PCH_SMBUS_HD1);
|
CallBuffer[0] = SmbusIoRead (R_PCH_SMBUS_HD0);
|
break;
|
|
case EfiSmbusReadByte:
|
if (*Length > 1) {
|
for (Index = 0; Index < *Length; Index++) {
|
///
|
/// Read the byte
|
///
|
CallBuffer[Index] = SmbusIoRead (R_PCH_SMBUS_HBD);
|
///
|
/// After receiving byte n-1 (1-base) of the message, the
|
/// software will then set the LAST BYTE bit. The software
|
/// will then clear the BYTE_DONE_STS bit.
|
///
|
if (Index == ((*Length - 1) - 1)) {
|
SmbusHctl = SmbusIoRead (R_PCH_SMBUS_HCTL) | (UINT8) B_PCH_SMBUS_LAST_BYTE;
|
SmbusIoWrite (R_PCH_SMBUS_HCTL, SmbusHctl);
|
} else if (Index == (*Length - 1)) {
|
///
|
/// Clear the LAST BYTE bit after receiving byte n (1-base) of the message
|
///
|
SmbusHctl = SmbusIoRead (R_PCH_SMBUS_HCTL) & (UINT8) ~B_PCH_SMBUS_LAST_BYTE;
|
SmbusIoWrite (R_PCH_SMBUS_HCTL, SmbusHctl);
|
}
|
///
|
/// Clear the BYTE_DONE_STS bit
|
///
|
SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BYTE_DONE_STS);
|
///
|
/// Check BYTE_DONE_STS bit to know if it has completed transmission
|
/// of a byte. No need to check it for the last byte.
|
///
|
if (Index < (*Length - 1)) {
|
///
|
/// If somehow board operates at 10Khz, it will take 0.9 ms (9/10Khz) for another byte.
|
/// Add 10 us delay for a loop of 100 that the total timeout is 1 ms to take care of
|
/// the slowest case.
|
///
|
for (Timeout = 0; Timeout < 100; Timeout++) {
|
if ((SmbusIoRead (R_PCH_SMBUS_HSTS) & (UINT8) B_PCH_SMBUS_BYTE_DONE_STS) != 0) {
|
break;
|
}
|
///
|
/// Delay 10 us
|
///
|
MicroSecondDelay (STALL_PERIOD);
|
}
|
|
if (Timeout >= 100) {
|
Status = EFI_TIMEOUT;
|
break;
|
}
|
}
|
}
|
break;
|
}
|
|
case EfiSmbusReceiveByte:
|
CallBuffer[0] = SmbusIoRead (R_PCH_SMBUS_HD0);
|
break;
|
|
case EfiSmbusWriteBlock:
|
SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BYTE_DONE_STS);
|
break;
|
|
case EfiSmbusReadBlock:
|
BufferTooSmall = FALSE;
|
///
|
/// Find out how many bytes will be in the block
|
///
|
BlockCount = SmbusIoRead (R_PCH_SMBUS_HD0);
|
if (*Length < BlockCount) {
|
BufferTooSmall = TRUE;
|
} else {
|
for (Index = 0; Index < BlockCount; Index++) {
|
///
|
/// Read the byte
|
///
|
CallBuffer[Index] = SmbusIoRead (R_PCH_SMBUS_HBD);
|
}
|
}
|
|
*Length = BlockCount;
|
if (BufferTooSmall) {
|
Status = EFI_BUFFER_TOO_SMALL;
|
}
|
break;
|
|
case EfiSmbusBWBRProcessCall:
|
///
|
/// Find out how many bytes will be in the block
|
///
|
BlockCount = SmbusIoRead (R_PCH_SMBUS_HD0);
|
///
|
/// The read byte count cannot be zero.
|
///
|
if (BlockCount < 1) {
|
Status = EFI_BUFFER_TOO_SMALL;
|
break;
|
}
|
///
|
/// The combined data payload (the write byte count + the read byte count)
|
/// must not exceed 32 bytes
|
///
|
if (((UINT8) (*Length) + BlockCount) > 32) {
|
Status = EFI_DEVICE_ERROR;
|
break;
|
}
|
|
for (Index = 0; Index < BlockCount; Index++) {
|
///
|
/// Read the byte
|
///
|
CallBuffer[Index] = SmbusIoRead (R_PCH_SMBUS_HBD);
|
}
|
|
*Length = BlockCount;
|
break;
|
|
default:
|
break;
|
};
|
|
if ((StsReg & B_PCH_SMBUS_BERR) && (Status != EFI_BUFFER_TOO_SMALL)) {
|
///
|
/// Clear the Bus Error for another try
|
///
|
Status = EFI_DEVICE_ERROR;
|
SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR);
|
///
|
/// If bus collision happens, stall some time, then try again
|
/// Here we choose 10 milliseconds to avoid MTCP transfer.
|
///
|
MicroSecondDelay (STALL_PERIOD);
|
continue;
|
} else {
|
break;
|
}
|
}
|
///
|
/// Clear Status Registers and exit
|
///
|
SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
|
SmbusIoWrite (R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE);
|
SmbusIoWrite (R_PCH_SMBUS_AUXC, 0);
|
return Status;
|
}
|
|
/**
|
This function initializes the Smbus Registers.
|
|
**/
|
VOID
|
InitializeSmbusRegisters (
|
VOID
|
)
|
{
|
UINTN SmbusRegBase;
|
|
SmbusRegBase = MmPciBase (
|
DEFAULT_PCI_BUS_NUMBER_PCH,
|
PCI_DEVICE_NUMBER_PCH_SMBUS,
|
PCI_FUNCTION_NUMBER_PCH_SMBUS
|
);
|
///
|
/// Enable the Smbus I/O Enable
|
///
|
MmioOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, (UINT8) EFI_PCI_COMMAND_IO_SPACE);
|
|
///
|
/// Enable the Smbus host controller
|
///
|
MmioAndThenOr8 (
|
SmbusRegBase + R_PCH_SMBUS_HOSTC,
|
(UINT8) (~(B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN)),
|
B_PCH_SMBUS_HOSTC_HST_EN
|
);
|
|
SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL);
|
}
|
