/** @file
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This file contains functions that configures PCI Express Root Ports function swapping.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MmPciLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/PchPcrLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/PchPciExpressHelpersLib.h>
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#include <Library/PchInitCommonLib.h>
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#include <Library/PchPsfPrivateLib.h>
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#include <Library/S3BootScriptLib.h>
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/**
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Configure root port function number mapping
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@retval EFI_SUCCESS The function completed successfully
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**/
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EFI_STATUS
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PchConfigureRpfnMapping (
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VOID
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)
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{
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UINT8 PortIndex;
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UINT8 OriginalFuncZeroRp;
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UINT8 MaxPciePortNum;
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UINT32 Data32;
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UINTN DevNum;
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UINTN FuncNum;
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UINTN RpBase;
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UINT32 ControllerPcd[PCH_MAX_PCIE_CONTROLLERS];
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PCH_SERIES PchSeries;
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PCH_GENERATION PchGen;
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UINT32 PcieControllers;
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UINT32 ControllerIndex;
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UINT32 FirstController;
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PCH_SBI_PID ControllerPid;
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DEBUG ((DEBUG_INFO,"PchConfigureRpfnMapping () Start\n"));
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PchSeries = GetPchSeries ();
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PchGen = GetPchGeneration ();
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MaxPciePortNum = GetPchMaxPciePortNum ();
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PcieControllers = GetPchMaxPcieControllerNum ();
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for (ControllerIndex = 0; ControllerIndex < PcieControllers; ++ControllerIndex) {
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PchPcrRead32 (PchGetPcieControllerSbiPid (ControllerIndex), R_PCH_PCR_SPX_PCD, &ControllerPcd[ControllerIndex]);
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}
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///
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/// Configure root port function number mapping
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///
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for (PortIndex = 0; PortIndex < MaxPciePortNum; ) {
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GetPchPcieRpDevFun (PortIndex, &DevNum, &FuncNum);
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RpBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, (UINT32) DevNum, (UINT32) FuncNum);
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//
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// Search for first enabled function
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//
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if (MmioRead16 (RpBase) != 0xFFFF) {
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if (FuncNum != 0) {
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//
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// First enabled root port that is not function zero will be swapped with function zero on the same device
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// RP PCD register must sync with PSF RP function config register
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//
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ControllerIndex = PortIndex / 4;
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OriginalFuncZeroRp = (PortIndex / 8) * 8;
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FirstController = OriginalFuncZeroRp / 4;
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//
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// The enabled root port becomes function zero
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//
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ControllerPcd[ControllerIndex] &= (UINT32) ~(B_PCH_PCR_SPX_PCD_RP1FN << ((PortIndex % 4) * S_PCH_PCR_SPX_PCD_RP_FIELD));
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ControllerPcd[ControllerIndex] |= 0u;
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//
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// Origianl function zero on the same device takes the numer of the current port
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//
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ControllerPcd[FirstController] &= (UINT32) ~B_PCH_PCR_SPX_PCD_RP1FN;
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ControllerPcd[FirstController] |= (UINT32) FuncNum;
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//
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// Program PSF1 RP function config register.
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//
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PsfSetPcieFunctionWithS3BootScript (OriginalFuncZeroRp, (UINT32) FuncNum);
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PsfSetPcieFunctionWithS3BootScript (PortIndex, 0);
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}
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//
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// Once enabled root port was found move to next PCI device
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//
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PortIndex = ((PortIndex / 8) + 1) * 8;
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continue;
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}
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//
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// Continue search for first enabled root port
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//
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PortIndex++;
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}
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//
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// Write to PCD and lock the register
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//
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for (ControllerIndex = 0; ControllerIndex < PcieControllers; ++ControllerIndex) {
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ControllerPid = PchGetPcieControllerSbiPid (ControllerIndex);
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Data32 = ControllerPcd[ControllerIndex] | B_PCH_PCR_SPX_PCD_SRL;
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PchPcrWrite32 (ControllerPid, R_PCH_PCR_SPX_PCD, Data32);
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PCH_PCR_BOOT_SCRIPT_WRITE (
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S3BootScriptWidthUint32,
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ControllerPid, R_PCH_PCR_SPX_PCD,
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1,
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&Data32
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);
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}
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return EFI_SUCCESS;
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}
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