/** @file
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Pch common library for PCH INIT PEI/DXE/SMM modules
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi/UefiBaseType.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/IoLib.h>
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#include <Library/MmPciLib.h>
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#include <PchAccess.h>
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#include <PchPolicyCommon.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchPcieRpLib.h>
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#include <Library/PchP2sbLib.h>
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#include <Library/PchSbiAccessLib.h>
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#include <Library/PchInfoLib.h>
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#include <Library/S3BootScriptLib.h>
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#include <Library/TimerLib.h>
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extern CONST PCH_PCIE_CONTROLLER_INFO mPchPcieControllerInfo[];
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extern CONST UINT32 mPchPcieControllerInfoSize;
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#define PORT_PLS_TIMEOUT 100 ///< 100 * 10 us = 1ms timeout for USB3 PortSC PLS polling
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/**
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This function returns PID according to PCIe controller index
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@param[in] ControllerIndex PCIe controller index
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
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PchGetPcieControllerSbiPid (
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IN UINT32 ControllerIndex
|
)
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{
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ASSERT (ControllerIndex < mPchPcieControllerInfoSize);
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return mPchPcieControllerInfo[ControllerIndex].Pid;
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}
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/**
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This function returns PID according to Root Port Number
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@param[in] RpIndex Root Port Index (0-based)
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@retval PCH_SBI_PID Returns PID for SBI Access
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**/
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PCH_SBI_PID
|
GetRpSbiPid (
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IN UINTN RpIndex
|
)
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{
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return PchGetPcieControllerSbiPid ((UINT32) (RpIndex / PCH_PCIE_CONTROLLER_PORTS));
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}
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/**
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Calculate root port device number based on physical port index.
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@param[in] RpIndex Root port index (0-based).
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@retval Root port device number.
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**/
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UINT32
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PchGetPcieRpDevice (
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IN UINT32 RpIndex
|
)
|
{
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UINTN ControllerIndex;
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ControllerIndex = RpIndex / PCH_PCIE_CONTROLLER_PORTS;
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ASSERT (ControllerIndex < mPchPcieControllerInfoSize);
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return mPchPcieControllerInfo[ControllerIndex].DevNum;
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}
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/**
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This function reads Pci Config register via SBI Access
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@param[in] RpIndex Root Port Index (0-based)
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@param[in] Offset Offset of Config register
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@param[out] *Data32 Value of Config register
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@retval EFI_SUCCESS SBI Read successful.
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**/
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EFI_STATUS
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PchSbiRpPciRead32 (
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IN UINT32 RpIndex,
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IN UINT32 Offset,
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OUT UINT32 *Data32
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)
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{
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EFI_STATUS Status;
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UINT32 RpDevice;
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UINT8 Response;
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UINT16 Fid;
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RpDevice = PchGetPcieRpDevice (RpIndex);
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Fid = (UINT16) ((RpDevice << 3) | (RpIndex % 4 ));
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Status = PchSbiExecutionEx (
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GetRpSbiPid (RpIndex),
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Offset,
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PciConfigRead,
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FALSE,
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0xF,
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0,
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Fid,
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Data32,
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&Response
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);
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if (Status != EFI_SUCCESS) {
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DEBUG ((DEBUG_ERROR,"Sideband Read Failed\n"));
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ASSERT (FALSE);
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}
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return Status;
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}
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/**
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This function And then Or Pci Config register via SBI Access
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@param[in] RpIndex Root Port Index (0-based)
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@param[in] Offset Offset of Config register
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@param[in] Data32And Value of Config register to be And-ed
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@param[in] Data32AOr Value of Config register to be Or-ed
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@retval EFI_SUCCESS SBI Read and Write successful.
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**/
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EFI_STATUS
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PchSbiRpPciAndThenOr32 (
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IN UINT32 RpIndex,
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IN UINT32 Offset,
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IN UINT32 Data32And,
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IN UINT32 Data32Or
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)
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{
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EFI_STATUS Status;
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UINT32 RpDevice;
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UINT32 Data32;
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UINT8 Response;
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UINT16 Fid;
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RpDevice = PchGetPcieRpDevice (RpIndex);
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Status = PchSbiRpPciRead32 (RpIndex, Offset, &Data32);
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if (Status == EFI_SUCCESS) {
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Data32 &= Data32And;
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Data32 |= Data32Or;
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Fid = (UINT16) ((RpDevice << 3) | (RpIndex % 4 ));
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Status = PchSbiExecutionEx (
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GetRpSbiPid (RpIndex),
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Offset,
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PciConfigWrite,
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FALSE,
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0xF,
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0,
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Fid,
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&Data32,
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&Response
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);
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if (Status != EFI_SUCCESS) {
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DEBUG ((DEBUG_ERROR,"Sideband Write Failed\n"));
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ASSERT (FALSE);
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}
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} else {
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ASSERT (FALSE);
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}
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return Status;
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}
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/**
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Check if RST PCIe Storage Remapping is enabled based on policy
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@param[in] RstPcieStorageRemap The PCH PCIe Storage remapping
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@retval TRUE RST PCIe Storage Remapping is enabled
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@retval FALSE RST PCIe Storage Remapping is disabled
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**/
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BOOLEAN
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IsRstPcieStorageRemapEnabled (
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IN CONST PCH_RST_PCIE_STORAGE_CONFIG *RstPcieStorageRemap
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)
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{
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BOOLEAN RstPcieStorageRemapEnabled;
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UINTN Index;
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RstPcieStorageRemapEnabled = FALSE;
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DEBUG ((DEBUG_INFO, "IsRstPcieStorageRemapEnabled Started\n"));
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for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) {
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if (RstPcieStorageRemap[Index].Enable == 1) {
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RstPcieStorageRemapEnabled = TRUE;
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}
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}
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DEBUG ((DEBUG_INFO, "IsRstPcieStorageRemapEnabled Ended\n"));
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return RstPcieStorageRemapEnabled;
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}
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/**
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Disable the RST remap address decoding range while RST is disabled.
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@param[in] AhciBar ABAR address
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**/
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VOID
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DisableRstRemapDecoding (
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UINT32 AhciBar
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)
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{
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UINTN PciSataRegBase;
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UINT32 OrgAhciBar;
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UINT8 OrgCmd;
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if (AhciBar == 0) {
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DEBUG ((DEBUG_ERROR, "DisableRstRemapDecoding: Invalid AHCI BAR address.\n"));
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ASSERT (FALSE);
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return;
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}
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PciSataRegBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA);
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OrgCmd = MmioRead8 (PciSataRegBase + PCI_COMMAND_OFFSET);
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OrgAhciBar = MmioRead32 (PciSataRegBase + R_PCH_SATA_AHCI_BAR);
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if (AhciBar != OrgAhciBar) {
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MmioWrite8 (PciSataRegBase + PCI_COMMAND_OFFSET, 0);
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MmioWrite32 (PciSataRegBase + R_PCH_SATA_AHCI_BAR, AhciBar);
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}
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MmioWrite8 (PciSataRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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//
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// Program "NVM Remap Memory BAR Enable", AHCIBar offset A4h [0] to ['0b']
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// Also set NRMO AHCIBar offset A4h [27:16] to 0x00F, and MSL AHCIBar offset A4h [12:1] to 0.
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//
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DEBUG ((DEBUG_INFO, "DisableRstRemapDecoding: Program AHCIBar offset A4h [27:16, 12:1, 0] to [0x00F, 0, 0] to disable remap decoding\n"));
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MmioWrite32 (AhciBar + R_PCH_SATA_VS_CAP, (0x00F << N_PCH_SATA_VS_CAP_NRMO));
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if (AhciBar != OrgAhciBar) {
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MmioWrite8 (PciSataRegBase + PCI_COMMAND_OFFSET, 0);
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MmioWrite32 (PciSataRegBase + R_PCH_SATA_AHCI_BAR, OrgAhciBar);
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}
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MmioWrite8 (PciSataRegBase + PCI_COMMAND_OFFSET, OrgCmd);
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}
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/**
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This function lock down the P2sb SBI before going into OS.
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@param[in] SbiUnlock
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**/
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VOID
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ConfigureP2sbSbiLock (
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IN CONST BOOLEAN SbiUnlock
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)
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{
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UINTN P2sbBase;
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BOOLEAN P2sbOrgStatus;
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if (SbiUnlock == FALSE) {
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P2sbBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_P2SB, PCI_FUNCTION_NUMBER_PCH_P2SB);
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PchRevealP2sb (P2sbBase, &P2sbOrgStatus);
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///
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/// Set P2SB PCI Offset 0xE0[31] to 1 to lock down SBI interface.
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/// @note: SbiLock is write once. Please make sure it's not touched earlier.
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///
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MmioOr8 (P2sbBase + R_PCH_P2SB_E0 + 3, BIT7);
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if (!P2sbOrgStatus) {
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PchHideP2sb (P2sbBase);
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}
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}
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}
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/**
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Bios will remove the host accessing right to Sideband register range
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prior to any 3rd party code execution.
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1) Set EPMASK5 Offset C4 (bits 29, 28, 27, 26, 17, 16 (PCH-LP only), 10, 1) to disable Sideband access for PSF and MIPI controller
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2) Set EPMASK7 Offset CC (bits 6, 5) to disable Sideband access for XHCI controller
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3) Set the "Endpoint Mask Lock!", P2SB PCI offset E2h bit[1] to 1.
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**/
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VOID
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RemoveSidebandAccess (
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VOID
|
)
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{
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UINTN P2sbBase;
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BOOLEAN P2sbOrgStatus;
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P2sbBase = MmPciBase (DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_P2SB, PCI_FUNCTION_NUMBER_PCH_P2SB);
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PchRevealP2sb (P2sbBase, &P2sbOrgStatus);
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//
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// Set EPMASK for ports B1, B0, AA, A1 (bits 17, 16 (PCH-LP only), 10, 1) to disable Sideband access for MIPI controller
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// Set EPMASK for ports BD, BC, BB, BA (bits 29, 28, 27, 26) to disable Sideband access for PCI Root Bridge
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//
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if (GetPchSeries () == PchLp) {
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MmioOr32 (P2sbBase + R_PCH_P2SB_EPMASK5, BIT29 | BIT28 | BIT27 | BIT26 | BIT17 | BIT16 | BIT10 | BIT1);
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} else {
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MmioOr32 (P2sbBase + R_PCH_P2SB_EPMASK5, BIT29 | BIT28 | BIT27 | BIT26 | BIT17 | BIT10 | BIT1);
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}
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//
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// Set EPMASK for ports E6, E5 (bits 6, 5) to disable Sideband access for XHCI controller
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//
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MmioOr32(P2sbBase + R_PCH_P2SB_EPMASK7, BIT6 | BIT5);
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DEBUG((DEBUG_INFO, "Lock the EPMASK registers\n"));
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MmioOr8 (P2sbBase + R_PCH_P2SB_E0 + 2, BIT1);
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if (!P2sbOrgStatus) {
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PchHideP2sb (P2sbBase);
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}
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}
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/**
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Configure PMC static function disable lock
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**/
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VOID
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ConfigurePmcStaticFunctionDisableLock (
|
VOID
|
)
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{
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UINT32 PchPwrmBase;
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PchPwrmBaseGet (&PchPwrmBase);
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|
MmioOr32 (PchPwrmBase + R_PCH_PWRM_ST_PG_FDIS_PMC_1, B_PCH_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK);
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}
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/**
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Print registers value
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@param[in] PrintMmioBase Mmio base address
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@param[in] PrintSize Number of registers
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@param[in] OffsetFromBase Offset from mmio base address
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@retval None
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**/
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VOID
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PrintRegisters (
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IN UINTN PrintMmioBase,
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IN UINT32 PrintSize,
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IN UINT32 OffsetFromBase
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)
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{
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UINT32 Offset;
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DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F"));
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for (Offset = 0; Offset < PrintSize; Offset++) {
|
if ((Offset % 16) == 0) {
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DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFFF0));
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}
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DEBUG ((DEBUG_VERBOSE, "%02X ", MmioRead8 (PrintMmioBase + Offset)));
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}
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DEBUG ((DEBUG_VERBOSE, "\n"));
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}
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VOID
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PrintPchPciConfigSpace (
|
VOID
|
)
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{
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 00 - 0 ] Host Bridge\n"));
|
PrintRegisters (MmPciBase ( 0,0,0 ), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 01 - 0 ] PCI Bridge (0-1) x16@1 (x16)\n"));
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PrintRegisters (MmPciBase ( 0,1,0 ), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 02 - 0 ] IGD\n"));
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PrintRegisters (MmPciBase ( 0,2,0 ), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 03 - 0 ] High Def Audio\n"));
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PrintRegisters (MmPciBase (00, 03, 00), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 20(0x14) - 0 ] XHCI Controller\n"));
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PrintRegisters (MmPciBase (00, 20, 00), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 22(0x16) - 0 ] ME\n"));
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PrintRegisters (MmPciBase (00, 22, 00), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 22(0x16) - 2 ] ME IDER\n"));
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PrintRegisters (MmPciBase (00, 22, 02), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 22(0x16) - 3 ] ME SOL\n"));
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PrintRegisters (MmPciBase (00, 22, 03), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 25(0x19) - 0 ] LAN\n"));
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PrintRegisters (MmPciBase (00, 25, 00), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 26(0x1A) - 0 ] EHCI Controller\n"));
|
PrintRegisters (MmPciBase (00, 26, 00), 256, 0);
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DEBUG ((DEBUG_VERBOSE, "[ 0 - 27(0x1B) - 0 ] High Def Audio\n"));
|
PrintRegisters (MmPciBase (00, 27, 00), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 28(0x1C) - 0 ] PCI Bridge (0-2) x0@1 (x1)\n"));
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PrintRegisters (MmPciBase (00, 28, 00), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "PCI Bridge: AECH\n"));
|
PrintRegisters (MmPciBase (00, 28, 00) + 0x0100, 0x040,0x0100);
|
DEBUG ((DEBUG_VERBOSE, "PCI Bridge: DFT\n"));
|
PrintRegisters (MmPciBase (00, 28, 00) + 0x0310, 0x030,0x0310);
|
DEBUG ((DEBUG_VERBOSE, "PCI Bridge: VC0\n"));
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PrintRegisters (MmPciBase (00, 28, 00) + 0x0340, 0x020,0x0340);
|
DEBUG ((DEBUG_VERBOSE, "PCI Bridge: Port Configuration Extension\n"));
|
PrintRegisters (MmPciBase (00, 28, 00) + 0x0400, 0x020,0x0400);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 28(0x1C) - 6 ] PCI Bridge (0-3:10) x0@1 (x1)\n"));
|
PrintRegisters (MmPciBase (00, 28, 06), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 29(0x1D) - 0 ] EHCI Controller\n"));
|
PrintRegisters (MmPciBase (00, 29, 00), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 31(0x1F) - 0 ] ISA Bridge\n"));
|
PrintRegisters (MmPciBase (00, 31, 00), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 31(0x1F) - 2 ] SATA\n"));
|
PrintRegisters (MmPciBase (00, 31, 02), 256, 0);
|
DEBUG ((DEBUG_VERBOSE, "[ 0 - 31(0x1F) - 4 ] SMBus Controller\n"));
|
PrintRegisters (MmPciBase (00, 31, 04), 256, 0);
|
|
DEBUG ((DEBUG_VERBOSE, "\n\n"));
|
}
|
|
/**
|
Program Xhci Port Disable Override
|
|
@param[in] XhciMmioBase xHCI controller MBAR0 address
|
@param[in] Usb2DisabledPorts Disabled USB2 ports where each port has its disabling bit
|
@param[in] Usb3DisabledPorts Disabled USB3 ports where each port has its disabling bit
|
|
@retval TRUE if platform reset is needed, otherwise FALSE is returned
|
**/
|
BOOLEAN
|
UsbPdoProgramming (
|
IN UINTN XhciMmioBase,
|
IN UINT32 Usb2DisabledPorts,
|
IN UINT32 Usb3DisabledPorts
|
)
|
{
|
UINT32 Index;
|
UINT32 XhciUsb2Pdo;
|
UINT32 XhciUsb3Pdo;
|
UINT32 XhciUsb2PdoRd;
|
UINT32 XhciUsb3PdoRd;
|
UINT32 XhciUsb3PortScStartingOffset;
|
UINT32 XhciUsb3PortScOffset;
|
UINT32 XhciPlsTimeout;
|
|
DEBUG ((DEBUG_INFO, "UsbPdoProgramming () start\n"));
|
DEBUG ((DEBUG_INFO, "xHCI: Usb2DisabledPorts = 0x%x\n", Usb2DisabledPorts));
|
DEBUG ((DEBUG_INFO, "xHCI: Usb3DisabledPorts = 0x%x\n", Usb3DisabledPorts));
|
|
//
|
// XHCI PDO for HS
|
//
|
if (GetPchSeries () == PchLp) {
|
XhciUsb2Pdo = MmioRead32 (XhciMmioBase + R_PCH_XHCI_USB2PDO) & B_PCH_XHCI_LP_USB2PDO_MASK;
|
} else {
|
XhciUsb2Pdo = MmioRead32 (XhciMmioBase + R_PCH_XHCI_USB2PDO) & B_PCH_XHCI_H_USB2PDO_MASK;
|
}
|
XhciUsb2Pdo |= Usb2DisabledPorts;
|
|
//
|
// XHCI PDO for SS
|
//
|
if (GetPchSeries () == PchLp) {
|
XhciUsb3Pdo = MmioRead32 (XhciMmioBase + R_PCH_XHCI_USB3PDO) & B_PCH_XHCI_LP_USB3PDO_MASK;
|
XhciUsb3PortScStartingOffset = R_PCH_LP_XHCI_PORTSC01USB3;
|
} else {
|
XhciUsb3Pdo = MmioRead32 (XhciMmioBase + R_PCH_XHCI_USB3PDO) & B_PCH_XHCI_H_USB3PDO_MASK;
|
XhciUsb3PortScStartingOffset = R_PCH_H_XHCI_PORTSC01USB3;
|
}
|
|
for (Index = 0; Index < GetPchXhciMaxUsb3PortNum (); Index++) {
|
// Check if port should be disabled
|
if ((Usb3DisabledPorts & (BIT0 << Index)) != 0) {
|
// Check if PDO bit has not been set yet
|
if (((XhciUsb3Pdo & (UINT32)(BIT0 << Index)) == 0)) {
|
// Calculate port PortSC register offset in xHCI MMIO space
|
XhciUsb3PortScOffset = (XhciUsb3PortScStartingOffset + (Index * 0x10));
|
|
// Disable port before setting PDO bit for it
|
MmioOr32 (XhciMmioBase + XhciUsb3PortScOffset, B_PCH_XHCI_PORTSCXUSB3_PED);
|
|
// Poll for PLS (PortSC[5:8]) to reach 0x4 before setting PDO for the port
|
for (XhciPlsTimeout = 0; XhciPlsTimeout < PORT_PLS_TIMEOUT; XhciPlsTimeout++) {
|
if ((MmioRead32 (XhciMmioBase + XhciUsb3PortScOffset) & B_PCH_XHCI_PORTSCXUSB3_PLS) == V_PCH_XHCI_PORTSCXUSB3_PLS_DISABLED) {
|
break;
|
}
|
MicroSecondDelay (10);
|
}
|
|
if (XhciPlsTimeout == PORT_PLS_TIMEOUT) {
|
DEBUG ((DEBUG_ERROR, "[xHCI PDO] PLS Polling for Disabled has timed out for port %d\n", Index + 1));
|
}
|
|
// A '1' in a bit position prevents the corresponding USB3 port from reporting a Device Connection to the XHC
|
XhciUsb3Pdo |= (UINT32) (B_PCH_XHCI_USB3PDO_DIS_PORT0 << Index);
|
|
// Put port back to RxDetect state
|
// Need to write LWS and PLS regs with same MMIO operation otherwise PLS write will be ignored
|
MmioOr32 (XhciMmioBase + XhciUsb3PortScOffset, (B_PCH_XHCI_PORTSCXUSB3_LWS | V_PCH_XHCI_PORTSCXUSB3_PLS_RXDETECT));
|
}
|
}
|
}
|
|
//
|
// USB2PDO and USB3PDO are Write-Once registers and bits in them are in the SUS Well.
|
//
|
MmioWrite32 (XhciMmioBase + R_PCH_XHCI_USB2PDO, XhciUsb2Pdo);
|
MmioWrite32 (XhciMmioBase + R_PCH_XHCI_USB3PDO, XhciUsb3Pdo);
|
|
XhciUsb2PdoRd = MmioRead32 (XhciMmioBase + R_PCH_XHCI_USB2PDO);
|
XhciUsb3PdoRd = MmioRead32 (XhciMmioBase + R_PCH_XHCI_USB3PDO);
|
|
//
|
// If USB2PDO and USB3PDO are not updated successfully perform Warm Reset to unlock RWO bits.
|
//
|
if ((XhciUsb2Pdo != XhciUsb2PdoRd) || (XhciUsb3Pdo != XhciUsb3PdoRd)) {
|
DEBUG ((DEBUG_ERROR, "UsbPdoProgramming: PDO register locked. Performing Warm Reset\n"));
|
return TRUE;
|
}
|
|
DEBUG ((DEBUG_INFO, "UsbPdoProgramming () end\n"));
|
return FALSE;
|
}
|
|
