/** @file
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This file contains SKL specific GPIO information
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <PchAccess.h>
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#include <Library/GpioLib.h>
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#include <Library/GpioNativeLib.h>
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#include <Library/GpioPrivateLib.h>
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#include <Pch/Library/PeiDxeSmmGpioLib/GpioLibrary.h>
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//
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// ISH GP pin
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshGPGpio[PCH_ISH_MAX_GP_PINS] =
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{
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{GPIO_SKL_LP_GPP_A18, GpioPadModeNative1},// ISH_GP_0
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{GPIO_SKL_LP_GPP_A19, GpioPadModeNative1},// ISH_GP_1
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{GPIO_SKL_LP_GPP_A20, GpioPadModeNative1},// ISH_GP_2
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{GPIO_SKL_LP_GPP_A21, GpioPadModeNative1},// ISH_GP_3
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{GPIO_SKL_LP_GPP_A22, GpioPadModeNative1},// ISH_GP_4
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{GPIO_SKL_LP_GPP_A23, GpioPadModeNative1},// ISH_GP_5
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{GPIO_SKL_LP_GPP_A12, GpioPadModeNative2},// ISH_GP_6
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{GPIO_SKL_LP_GPP_A17, GpioPadModeNative2} // ISH_GP_7
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};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshGPGpio[PCH_ISH_MAX_GP_PINS] =
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{
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{GPIO_SKL_H_GPP_A18, GpioPadModeNative1},// ISH_GP_0
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{GPIO_SKL_H_GPP_A19, GpioPadModeNative1},// ISH_GP_1
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{GPIO_SKL_H_GPP_A20, GpioPadModeNative1},// ISH_GP_2
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{GPIO_SKL_H_GPP_A21, GpioPadModeNative1},// ISH_GP_3
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{GPIO_SKL_H_GPP_A22, GpioPadModeNative1},// ISH_GP_4
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{GPIO_SKL_H_GPP_A23, GpioPadModeNative1},// ISH_GP_5
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{GPIO_SKL_H_GPP_A12, GpioPadModeNative2},// ISH_GP_6
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{GPIO_SKL_H_GPP_A17, GpioPadModeNative1} // ISH_GP_7
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};
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//
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// ISH UART controller pins
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// ISH UART[controller number][pin: RXD/TXD/RTSB/CTSB]
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshUartGpio[PCH_ISH_MAX_UART_CONTROLLERS][PCH_ISH_PINS_PER_UART_CONTROLLER] =
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{
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{ //UART0
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{GPIO_SKL_LP_GPP_D13, GpioPadModeNative1},// ISH_UART0_RXD
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{GPIO_SKL_LP_GPP_D14, GpioPadModeNative1},// ISH_UART0_TXD
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{GPIO_SKL_LP_GPP_D15, GpioPadModeNative1},// ISH_UART0_RTS
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{GPIO_SKL_LP_GPP_D16, GpioPadModeNative1} // ISH_UART0_CTS
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},
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{ //UART1
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{GPIO_SKL_LP_GPP_C12, GpioPadModeNative2},// ISH_UART1_RXD
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{GPIO_SKL_LP_GPP_C13, GpioPadModeNative2},// ISH_UART1_TXD
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{GPIO_SKL_LP_GPP_C14, GpioPadModeNative2},// ISH_UART1_RTSB
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{GPIO_SKL_LP_GPP_C15, GpioPadModeNative2} // ISH_UART1_CTSB
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}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshUartGpio[PCH_ISH_MAX_UART_CONTROLLERS][PCH_ISH_PINS_PER_UART_CONTROLLER] =
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{
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{ //UART0
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{GPIO_SKL_H_GPP_D13, GpioPadModeNative1},// ISH_UART0_RXD
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{GPIO_SKL_H_GPP_D14, GpioPadModeNative1},// ISH_UART0_TXD
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{GPIO_SKL_H_GPP_D15, GpioPadModeNative1},// ISH_UART0_RTS
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{GPIO_SKL_H_GPP_D16, GpioPadModeNative1} // ISH_UART0_CTS
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},
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{ //UART1
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{GPIO_SKL_H_GPP_C12, GpioPadModeNative2},// ISH_UART1_RXD
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{GPIO_SKL_H_GPP_C13, GpioPadModeNative2},// ISH_UART1_TXD
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{GPIO_SKL_H_GPP_C14, GpioPadModeNative2},// ISH_UART1_RTS
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{GPIO_SKL_H_GPP_C15, GpioPadModeNative2} // ISH_UART1_CTS
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}
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};
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//
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// ISH I2C controller pins
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// ISH I2C[controller number][pin: SDA/SCL]
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshI2cGpio[PCH_ISH_MAX_I2C_CONTROLLERS][PCH_ISH_PINS_PER_I2C_CONTROLLER] =
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{
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{ //I2C0
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{GPIO_SKL_LP_GPP_D5, GpioPadModeNative1},// ISH_I2C0_SDA
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{GPIO_SKL_LP_GPP_D6, GpioPadModeNative1} // ISH_I2C0_SCL
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},
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{ //I2C1
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{GPIO_SKL_LP_GPP_D7, GpioPadModeNative1},// ISH_I2C1_SDA
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{GPIO_SKL_LP_GPP_D8, GpioPadModeNative1} // ISH_I2C1_SCL
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},
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{ //I2C2
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{GPIO_SKL_LP_GPP_F10, GpioPadModeNative2},// ISH_I2C2_SDA
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{GPIO_SKL_LP_GPP_F11, GpioPadModeNative2} // ISH_I2C2_SCL
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}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshI2cGpio[PCH_ISH_MAX_I2C_CONTROLLERS][PCH_ISH_PINS_PER_I2C_CONTROLLER] =
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{
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{ //I2C0
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{GPIO_SKL_H_GPP_H19, GpioPadModeNative1},// ISH_I2C0_SDA
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{GPIO_SKL_H_GPP_H20, GpioPadModeNative1} // ISH_I2C0_SCL
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},
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{ //I2C1
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{GPIO_SKL_H_GPP_H21, GpioPadModeNative1},// ISH_I2C1_SDA
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{GPIO_SKL_H_GPP_H22, GpioPadModeNative1} // ISH_I2C1_SCL
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},
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{ //I2C2
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{GPIO_SKL_H_GPP_D4, GpioPadModeNative1},// ISH_I2C2_SDA
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{GPIO_SKL_H_GPP_D23, GpioPadModeNative1} // ISH_I2C2_SCL
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}
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};
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//
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// ISH SPI controller pins
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// ISH SPI[pin: CSB/CLK/MISO/MOSI]
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshSpiGpio[PCH_ISH_PINS_PER_SPI_CONTROLLER] =
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{
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{GPIO_SKL_LP_GPP_D9, GpioPadModeNative1},// ISH_SPI_CSB
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{GPIO_SKL_LP_GPP_D10, GpioPadModeNative1},// ISH_SPI_CLK
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{GPIO_SKL_LP_GPP_D11, GpioPadModeNative1},// ISH_SPI_MISO
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{GPIO_SKL_LP_GPP_D12, GpioPadModeNative1} // ISH_SPI_MOSI
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};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshSpiGpio[PCH_ISH_PINS_PER_SPI_CONTROLLER] =
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{
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{GPIO_SKL_H_GPP_D9, GpioPadModeNative1},// ISH_SPI_CSB
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{GPIO_SKL_H_GPP_D10, GpioPadModeNative1},// ISH_SPI_CLK
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{GPIO_SKL_H_GPP_D11, GpioPadModeNative1},// ISH_SPI_MISO
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{GPIO_SKL_H_GPP_D12, GpioPadModeNative1} // ISH_SPI_MOSI
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};
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//
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// GPIO pin for PCIE SCRCLKREQB
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// SCRCLKREQB_x -> GPIO pin y
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpPcieSrcClkReqbPinToGpioMap[PCH_LP_PCIE_MAX_CLK_REQ] =
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{
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{GPIO_SKL_LP_GPP_B5, GpioPadModeNative1},
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{GPIO_SKL_LP_GPP_B6, GpioPadModeNative1},
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{GPIO_SKL_LP_GPP_B7, GpioPadModeNative1},
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{GPIO_SKL_LP_GPP_B8, GpioPadModeNative1},
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{GPIO_SKL_LP_GPP_B9, GpioPadModeNative1},
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{GPIO_SKL_LP_GPP_B10, GpioPadModeNative1}
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};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHPcieSrcClkReqbPinToGpioMap[PCH_H_PCIE_MAX_CLK_REQ] =
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{
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{GPIO_SKL_H_GPP_B5, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_B6, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_B7, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_B8, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_B9, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_B10, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H0, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H1, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H2, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H3, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H4, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H5, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H6, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H7, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H8, GpioPadModeNative1},
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{GPIO_SKL_H_GPP_H9, GpioPadModeNative1}
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};
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//
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// PCHHOTB pin
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpPchHotbPin = {GPIO_SKL_LP_GPP_B23, GpioPadModeNative2};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHPchHotbPin = {GPIO_SKL_H_GPP_B23, GpioPadModeNative2};
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//
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// CPU GP pins
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//
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCpuGpPinMap[4] =
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{
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{GPIO_SKL_LP_GPP_E3, GpioPadModeNative1}, // CPU_GP_0
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{GPIO_SKL_LP_GPP_E7, GpioPadModeNative1}, // CPU_GP_1
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{GPIO_SKL_LP_GPP_B3, GpioPadModeNative1}, // CPU_GP_2
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{GPIO_SKL_LP_GPP_B4, GpioPadModeNative1}, // CPU_GP_3
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};
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GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCpuGpPinMap[4] =
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{
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{GPIO_SKL_H_GPP_E3, GpioPadModeNative1}, // CPU_GP_0
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{GPIO_SKL_H_GPP_E7, GpioPadModeNative1}, // CPU_GP_1
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{GPIO_SKL_H_GPP_B3, GpioPadModeNative1}, // CPU_GP_2
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{GPIO_SKL_H_GPP_B4, GpioPadModeNative1}, // CPU_GP_3
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};
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