/** @file
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This file contains routines for GPIO native and chipset specific purpose
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used by Reference Code only.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Base.h>
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#include <Uefi/UefiBaseType.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <PchAccess.h>
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#include <Library/GpioLib.h>
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#include <Library/GpioNativeLib.h>
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#include <Library/GpioPrivateLib.h>
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#include <Library/PchInfoLib.h>
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#include <Pch/Library/PeiDxeSmmGpioLib/GpioLibrary.h>
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//
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// Chipset specific data
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//
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//ISH
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpIshGPGpio[PCH_ISH_MAX_GP_PINS];
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extern GPIO_PAD_NATIVE_FUNCTION mPchHIshGPGpio[PCH_ISH_MAX_GP_PINS];
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpIshI2cGpio[PCH_ISH_MAX_I2C_CONTROLLERS][PCH_ISH_PINS_PER_I2C_CONTROLLER];
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extern GPIO_PAD_NATIVE_FUNCTION mPchHIshI2cGpio[PCH_ISH_MAX_I2C_CONTROLLERS][PCH_ISH_PINS_PER_I2C_CONTROLLER];
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpIshUartGpio[PCH_ISH_MAX_UART_CONTROLLERS][PCH_ISH_PINS_PER_UART_CONTROLLER];
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extern GPIO_PAD_NATIVE_FUNCTION mPchHIshUartGpio[PCH_ISH_MAX_UART_CONTROLLERS][PCH_ISH_PINS_PER_UART_CONTROLLER];
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpIshSpiGpio[PCH_ISH_PINS_PER_SPI_CONTROLLER];
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extern GPIO_PAD_NATIVE_FUNCTION mPchHIshSpiGpio[PCH_ISH_PINS_PER_SPI_CONTROLLER];
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//PCIe SRCCLKREQB
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpPcieSrcClkReqbPinToGpioMap[PCH_LP_PCIE_MAX_CLK_REQ];
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extern GPIO_PAD_NATIVE_FUNCTION mPchHPcieSrcClkReqbPinToGpioMap[PCH_H_PCIE_MAX_CLK_REQ];
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//PCH_HOT
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpPchHotbPin;
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extern GPIO_PAD_NATIVE_FUNCTION mPchHPchHotbPin;
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//CPU GP
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extern GPIO_PAD_NATIVE_FUNCTION mPchLpCpuGpPinMap[4];
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extern GPIO_PAD_NATIVE_FUNCTION mPchHCpuGpPinMap[4];
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/**
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This function sets ISH I2C controller pins into native mode
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@param[in] IshI2cControllerNumber I2C controller
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@retval Status
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**/
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EFI_STATUS
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GpioSetIshI2cPinsIntoNativeMode (
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IN UINT32 IshI2cControllerNumber
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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GPIO_PAD_NATIVE_FUNCTION (*I2cGpio) [PCH_ISH_PINS_PER_I2C_CONTROLLER];
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Status = EFI_SUCCESS;
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if (GetPchSeries () == PchLp) {
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I2cGpio = mPchLpIshI2cGpio;
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} else {
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I2cGpio = mPchHIshI2cGpio;
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}
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ASSERT (IshI2cControllerNumber < PCH_ISH_MAX_I2C_CONTROLLERS);
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for (Index = 0; Index < PCH_ISH_PINS_PER_I2C_CONTROLLER; Index++) {
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Status = SetGpioPadMode (I2cGpio[IshI2cControllerNumber][Index].Pad, I2cGpio[IshI2cControllerNumber][Index].Mode);
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if (EFI_ERROR (Status)) {
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return EFI_UNSUPPORTED;
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}
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}
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return Status;
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}
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/**
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This function sets ISH UART controller pins into native mode
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@param[in] IshUartControllerNumber UART controller
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@retval Status
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**/
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EFI_STATUS
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GpioSetIshUartPinsIntoNativeMode (
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IN UINT32 IshUartControllerNumber
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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GPIO_PAD_NATIVE_FUNCTION (*UartGpio) [PCH_ISH_PINS_PER_UART_CONTROLLER];
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Status = EFI_SUCCESS;
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if (GetPchSeries () == PchLp) {
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UartGpio = mPchLpIshUartGpio;
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} else {
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UartGpio = mPchHIshUartGpio;
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}
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ASSERT (IshUartControllerNumber < PCH_ISH_MAX_UART_CONTROLLERS);
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for (Index = 0; Index < PCH_ISH_PINS_PER_UART_CONTROLLER; Index++) {
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Status = SetGpioPadMode (UartGpio[IshUartControllerNumber][Index].Pad, UartGpio[IshUartControllerNumber][Index].Mode);
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if (EFI_ERROR (Status)) {
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return EFI_UNSUPPORTED;
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}
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}
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return Status;
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}
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/**
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This function sets ISH SPI controller pins into native mode
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@param[in] none
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@retval Status
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**/
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EFI_STATUS
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GpioSetIshSpiPinsIntoNativeMode (
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VOID
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)
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{
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EFI_STATUS Status;
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UINTN Index;
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GPIO_PAD_NATIVE_FUNCTION *SpiGpio;
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Status = EFI_SUCCESS;
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if (GetPchSeries () == PchLp) {
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SpiGpio = mPchLpIshSpiGpio;
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} else {
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SpiGpio = mPchHIshSpiGpio;
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}
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for (Index = 0; Index < PCH_ISH_PINS_PER_SPI_CONTROLLER; Index++) {
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Status = SetGpioPadMode (SpiGpio[Index].Pad, SpiGpio[Index].Mode);
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if (EFI_ERROR (Status)) {
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return EFI_UNSUPPORTED;
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}
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}
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return Status;
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}
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/**
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This function sets ISH GP pins into native mode
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@param[in] IshGpPinNumber ISH GP pin number
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@retval Status
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**/
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EFI_STATUS
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GpioSetIshGpPinsIntoNativeMode (
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IN UINT32 IshGpPinNumber
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)
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{
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EFI_STATUS Status;
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GPIO_PAD_NATIVE_FUNCTION *IshGp;
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Status = EFI_SUCCESS;
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if (GetPchSeries () == PchLp) {
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IshGp = mPchLpIshGPGpio;
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} else {
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IshGp = mPchHIshGPGpio;
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}
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ASSERT (IshGpPinNumber < PCH_ISH_MAX_GP_PINS);
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Status = SetGpioPadMode (IshGp[IshGpPinNumber].Pad, IshGp[IshGpPinNumber].Mode);
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if (EFI_ERROR (Status)) {
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return EFI_UNSUPPORTED;
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}
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return Status;
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}
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/**
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Returns a pad for given CLKREQ# index.
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@param[in] ClkreqIndex CLKREQ# number
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@return CLKREQ# pad.
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**/
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GPIO_PAD
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GpioGetClkreqPad (
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IN UINT32 ClkreqIndex
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)
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{
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if (GetPchSeries () == PchLp) {
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ASSERT (ClkreqIndex < PCH_LP_PCIE_MAX_CLK_REQ);
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return mPchLpPcieSrcClkReqbPinToGpioMap[ClkreqIndex].Pad;
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} else {
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ASSERT (ClkreqIndex < PCH_H_PCIE_MAX_CLK_REQ);
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return mPchHPcieSrcClkReqbPinToGpioMap[ClkreqIndex].Pad;
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}
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}
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/**
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Enables CLKREQ# pad in native mode.
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@param[in] ClkreqIndex CLKREQ# number
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@return none
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**/
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VOID
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GpioEnableClkreq (
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IN UINT32 ClkreqIndex
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)
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{
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GPIO_CONFIG PadConfig;
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GPIO_PAD ClkreqPad;
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GPIO_PAD_MODE PadMode;
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ZeroMem (&PadConfig, sizeof (PadConfig));
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if (GetPchSeries () == PchLp) {
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ASSERT (ClkreqIndex < PCH_LP_PCIE_MAX_CLK_REQ);
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ClkreqPad = mPchLpPcieSrcClkReqbPinToGpioMap[ClkreqIndex].Pad;
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PadMode = mPchLpPcieSrcClkReqbPinToGpioMap[ClkreqIndex].Mode;
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} else {
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ASSERT (ClkreqIndex < PCH_H_PCIE_MAX_CLK_REQ);
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ClkreqPad = mPchHPcieSrcClkReqbPinToGpioMap[ClkreqIndex].Pad;
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PadMode = mPchHPcieSrcClkReqbPinToGpioMap[ClkreqIndex].Mode;
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}
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PadConfig.PadMode = PadMode;
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PadConfig.Direction = GpioDirNone;
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PadConfig.PowerConfig = GpioHostDeepReset;
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DEBUG ((DEBUG_INFO, "Enabling CLKREQ%d\n", ClkreqIndex));
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GpioSetPadConfig (ClkreqPad, &PadConfig);
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}
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/**
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This function checks if GPIO pin for PCHHOTB is in NATIVE MODE
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@param[in] none
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@retval TRUE Pin is in PCHHOTB native mode
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FALSE Pin is in gpio mode or is not owned by HOST
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**/
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BOOLEAN
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GpioIsPchHotbPinInNativeMode (
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VOID
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)
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{
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EFI_STATUS Status;
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GPIO_PAD_NATIVE_FUNCTION PchHotbPin;
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GPIO_PAD_MODE GpioMode;
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if (GetPchSeries () == PchLp) {
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PchHotbPin = mPchLpPchHotbPin;
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} else {
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PchHotbPin = mPchHPchHotbPin;
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}
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Status = GetGpioPadMode (PchHotbPin.Pad, &GpioMode);
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if ((EFI_ERROR (Status)) || (GpioMode != PchHotbPin.Mode)) {
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return FALSE;
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} else {
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return TRUE;
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}
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}
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/**
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This function sets CPU GP pins into native mode
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@param[in] CpuGpPinNum CPU GP pin number
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@retval Status
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**/
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EFI_STATUS
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GpioSetCpuGpPinsIntoNativeMode (
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IN UINT32 CpuGpPinNum
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)
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{
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EFI_STATUS Status;
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GPIO_PAD_NATIVE_FUNCTION *CpuGpPins;
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if (GetPchSeries () == PchLp) {
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CpuGpPins = mPchLpCpuGpPinMap;
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} else {
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CpuGpPins = mPchHCpuGpPinMap;
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}
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ASSERT (CpuGpPinNum < 4);
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Status = SetGpioPadMode (CpuGpPins[CpuGpPinNum].Pad, CpuGpPins[CpuGpPinNum].Mode);
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if (EFI_ERROR (Status)) {
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return EFI_UNSUPPORTED;
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}
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return EFI_SUCCESS;
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}
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