/** @file
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Implement the I2C controller driver.
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <Uefi.h>
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#include <Base.h>
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#include <IndustryStandard/Pci.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/TimerLib.h>
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#include <Library/UefiLib.h>
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#include <PchAccess.h>
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#include <Library/PchSerialIoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Protocol/I2cMaster.h>
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#include <Pi/PiI2c.h>
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#include <Library/DevicePathLib.h>
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#include <Library/I2cMasterCommonLib.h>
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/**
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Prepare I2c controller for use: enable its mmio range, put in D0, get out of reset
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@param[in] Context - driver context
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**/
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VOID
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PrepareController (
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I2C_MASTER_CONTEXT *Context
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)
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{
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MmioOr32 (Context->ConfigAddress + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER);
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MmioAnd32 (Context->ConfigAddress + R_PCH_SERIAL_IO_PME_CTRL_STS, (UINT32) (~B_PCH_SERIAL_IO_PME_CTRL_STS_PWR_ST));
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MmioOr32 (Context->MmioAddress + R_PCH_SERIAL_IO_PPR_RESETS,
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B_PCH_SERIAL_IO_PPR_RESETS_FUNC | B_PCH_SERIAL_IO_PPR_RESETS_APB | B_PCH_SERIAL_IO_PPR_RESETS_IDMA);
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}
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/**
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Determine the state of the I2C controller
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@param[in] Context - driver context
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@retval TRUE The I2C controller is active
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@retval FALSE The I2C controller is idle
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**/
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BOOLEAN
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IsHardwareActive (
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I2C_MASTER_CONTEXT *Context
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)
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{
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return (MmioRead32 (Context->MmioAddress + R_IC_STATUS) & B_IC_STATUS_ACTIVITY );
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}
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/**
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Updates WriteOperation and WritePosition, two variables that determine
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which part of Request is being committed to I2C bus.
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This iterates over both Read and Write operations from a request, because
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things that need to be written to WriteFifo are both I2c bus writes
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and I2c bus reads (the command to perform bus read needs to be put into Write Fifo)
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@param[in] Context - driver context
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**/
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VOID
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UpdateWritePosition (
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I2C_MASTER_CONTEXT *Context
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)
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{
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if ( Context->WritePos == Context->Request->Operation[Context->WriteOp].LengthInBytes - 1) {
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Context->WritePos = 0;
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Context->WriteOp ++;
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} else {
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Context->WritePos ++;
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}
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}
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/*
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FindReadOp checks if current Operation is of Read type. If so, returns.
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If not, increases ReadOp until it finds one or goes beyond Request's OperationCount
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@param[in] Context - driver context
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*/
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VOID
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FindReadOp (
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I2C_MASTER_CONTEXT *Context
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)
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{
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while (Context->ReadOp < Context->Request->OperationCount &&
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!(Context->Request->Operation[Context->ReadOp].Flags & I2C_FLAG_READ)) {
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Context->ReadOp++;
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}
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}
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/**
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Updates ReadOperation and ReadPosition, two variables that determine
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which part of Request is being filled with data incoming from I2C reads.
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This iterates only over Read operations from a request.
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@param[in] Context - driver context
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**/
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VOID
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UpdateReadPosition (
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I2C_MASTER_CONTEXT *Context
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)
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{
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if ( Context->ReadPos == Context->Request->Operation[Context->ReadOp].LengthInBytes - 1) {
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Context->ReadPos = 0;
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Context->ReadOp ++;
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FindReadOp (Context);
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} else {
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Context->ReadPos ++;
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}
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}
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/**
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ValidateRequest checks if Request is valid and can be started
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@param[in] Context - driver context
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@param[in] RequestPacket
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@retval EFI_SUCCESS Request is valid and can be started
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@retval EFI_ALREADY_STARTED The controller is busy with another transfer
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@retval EFI_BAD_BUFFER_SIZE Transfer size too big
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@retval EFI_INVALID_PARAMETER RequestPacket is NULL, invalid Operation flags
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@retval EFI_UNSUPPORTED "ping" operation attempted (0-byte transfer, address byte not followed by any data)
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**/
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EFI_STATUS
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ValidateRequest (
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I2C_MASTER_CONTEXT *Context,
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CONST EFI_I2C_REQUEST_PACKET *RequestPacket
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)
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{
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UINTN TotalSize;
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UINTN Operation;
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UINTN OperationSize;
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if (Context->TransferInProgress) {
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return EFI_ALREADY_STARTED;
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}
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if (RequestPacket == NULL) {
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return EFI_INVALID_PARAMETER;
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}
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if (RequestPacket->OperationCount == 0) {
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// 0-size operations ("pings") not supported
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return EFI_UNSUPPORTED;
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}
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TotalSize = 0;
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for (Operation=0; Operation < RequestPacket->OperationCount; Operation++) {
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// unsupported flags?
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if ((RequestPacket->Operation[Operation].Flags & (~I2C_FLAG_READ)) != 0) {
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return EFI_INVALID_PARAMETER;
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}
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OperationSize = RequestPacket->Operation[Operation].LengthInBytes;
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// 0-size operations ("pings") not supported
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if (OperationSize == 0) {
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return EFI_UNSUPPORTED;
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}
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TotalSize += OperationSize;
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// read operation too big?
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if (RequestPacket->Operation[Operation].Flags & I2C_FLAG_READ) {
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if (OperationSize > Context->Capabilities.MaximumReceiveBytes) {
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return EFI_BAD_BUFFER_SIZE;
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}
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// write operation too big?
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} else {
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if (OperationSize > Context->Capabilities.MaximumTransmitBytes) {
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return EFI_BAD_BUFFER_SIZE;
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}
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}
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}
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// total request too big?
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if (TotalSize > Context->Capabilities.MaximumTotalBytes) {
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return EFI_BAD_BUFFER_SIZE;
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}
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return EFI_SUCCESS;
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}
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/**
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IsLastFromRequest checks if WritePos and WriteOp point to the last byte of the request
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@param[in] Context - driver context
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@retval Boolean
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**/
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BOOLEAN
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IsLastFromRequest (
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I2C_MASTER_CONTEXT *Context
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)
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{
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if ((Context->WriteOp == Context->Request->OperationCount - 1 ) &&
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(Context->WritePos == Context->Request->Operation[Context->WriteOp].LengthInBytes - 1)) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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/**
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IsFirstFromOperation checks if WritePos and WriteOp point to the first byte of an operation
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@param[in] Context - driver context
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@retval Boolean
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**/
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BOOLEAN
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IsFirstFromOperation (
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I2C_MASTER_CONTEXT *Context
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)
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{
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if ((Context->WriteOp != 0) && (Context->WritePos == 0)) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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/**
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InitializeTransfer checks if HW is ready to accept new transfer.
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If so, sets up slave address
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@param[in] Context - driver context
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@retval Status
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**/
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EFI_STATUS
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InitializeTransfer (
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I2C_MASTER_CONTEXT *Context,
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UINTN SlaveAddress,
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CONST EFI_I2C_REQUEST_PACKET *RequestPacket
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)
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{
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UINT32 Attempts = 10000;
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UINT32 Address;
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Context->Request = (EFI_I2C_REQUEST_PACKET*) RequestPacket;
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Context->TransferStatus = EFI_SUCCESS;
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Context->WriteOp = 0;
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Context->WritePos = 0;
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Context->ReadOp = 0;
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FindReadOp (Context);
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Context->ReadPos = 0;
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if (MmioRead32 (Context->MmioAddress + R_IC_ENABLE) != 0) {
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DEBUG (( DEBUG_ERROR, "Address change was attempted while a transfer was underway!\n"));
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return EFI_DEVICE_ERROR;
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}
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Address = SlaveAddress & 0xFF;
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if (SlaveAddress & I2C_ADDRESSING_10_BIT
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) {
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Address |= B_IC_TAR_10BITADDR_MASTER;
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}
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MmioWrite32 (Context->MmioAddress + R_IC_TAR, Address);
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MmioWrite32 (Context->MmioAddress + R_IC_ENABLE, B_IC_EN );
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//clear errors
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MmioRead32 (Context->MmioAddress + R_IC_CLR_TX_ABRT);
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MmioRead32 (Context->MmioAddress + R_IC_CLR_INTR);
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while ( !(MmioRead32 (Context->MmioAddress + R_IC_ENABLE_STATUS ) & B_IC_EN)) {
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//should never happen, but just to make sure BIOS doesn't hang in infinite loop...
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MicroSecondDelay (1);
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if (--Attempts == 0) {
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MmioWrite32 (Context->MmioAddress + R_IC_ENABLE, 0 );
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return EFI_DEVICE_ERROR;
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}
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}
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Context->TransferInProgress = TRUE;
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return EFI_SUCCESS;
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}
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/**
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WriteFifo writes to I2c controller's transmit Fifo. Data written to Fifo could be
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- data bytes to be written to an i2c slave
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- read requests that trigger i2c bus reads
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First transfer from each operation adds Restart bit which triggers Restart condition on bus
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Last transfer from the whole Request adds Stop bit which triggers Stop condtion on bus
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Driver keeps track of which parts of Request were already committed to hardware using
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pointer consisting of WritePosition and WriteOperation variables. This pointer is updated
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every time data byte/read request is committed to FIFO
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WriteFifo executes while there's anything more to write and the write fifo isn't full
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@param[in] Context - driver context
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**/
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VOID
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WriteFifo (
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I2C_MASTER_CONTEXT *Context
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)
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{
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UINT32 Data;
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while ( MmioRead32 (Context->MmioAddress + R_IC_STATUS ) & B_IC_STATUS_TFNF) {
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if (Context->WriteOp >= Context->Request->OperationCount ) {
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return; // request complete, nothing more to write
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}
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if (Context->Request->Operation[Context->WriteOp].Flags & I2C_FLAG_READ) {
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Data = B_IC_CMD_READ;
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} else {
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Data = Context->Request->Operation[Context->WriteOp].Buffer[Context->WritePos];
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}
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if (IsLastFromRequest (Context)) {
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Data |= B_IC_CMD_STOP;
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}
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if (IsFirstFromOperation (Context)) {
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Data |= B_IC_CMD_RESTART;
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}
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MmioWrite32 (Context->MmioAddress + R_IC_DATA_CMD, Data);
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UpdateWritePosition (Context);
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}
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}
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/**
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ReadFifo reads from I2c controller's receive Fifo. It contains data retrieved
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from slave device as a result of executing read transfers, which were
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triggered by putting read requests into Write Fifo. Retrieved data is copied into buffers
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pointed to by Request structure.
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Driver keeps track where to copy incoming data using pointer consisting of
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ReadPosition and ReadOperation variables. This pointer is updated
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every time data was retrieved from hardware
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ReadFifo executes while there's data available and receive buffers were not filled
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@param[in] Context - driver context
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**/
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VOID
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ReadFifo (
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I2C_MASTER_CONTEXT *Context
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)
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{
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while ( MmioRead32 ( Context->MmioAddress + R_IC_STATUS ) & B_IC_STATUS_RFNE) {
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if ( Context->ReadOp >= Context->Request->OperationCount ) {
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return;
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}
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Context->Request->Operation[Context->ReadOp].Buffer[Context->ReadPos] = (0xFF & MmioRead32 (Context->MmioAddress + R_IC_DATA_CMD));
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UpdateReadPosition (Context);
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}
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}
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/**
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CheckErrors checks if there were any transfer errors.
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@param[in] Context - driver context
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**/
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VOID
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CheckErrors (
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I2C_MASTER_CONTEXT *Context
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)
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{
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if (!(MmioRead32 (Context->MmioAddress + R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT)) {
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return;
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}
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if (MmioRead32 (Context->MmioAddress + R_IC_TX_ABRT_SOURCE) & B_IC_TX_ABRT_7B_ADDR_NACK) {
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Context->TransferStatus = EFI_NO_RESPONSE;
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} else {
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Context->TransferStatus = EFI_DEVICE_ERROR;
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}
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DEBUG (( DEBUG_INFO, "I2c CheckErrors: %08x\n", MmioRead32 (Context->MmioAddress + R_IC_TX_ABRT_SOURCE)));
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}
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/**
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Transfer is finished when all requested operations were placed in fifo,
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all read requests were filled and hardware is inactive
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The last part is necessary for write-only transfers where after
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placing all writes in fifo sw needs to wait until they flush down the bus
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@param[in] Context - driver context
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@retval Boolean
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**/
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BOOLEAN
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IsTransferFinished (
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I2C_MASTER_CONTEXT *Context
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)
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{
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if (( Context->WriteOp >= Context->Request->OperationCount ) &&
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( Context->ReadOp >= Context->Request->OperationCount ) &&
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!IsHardwareActive (Context)) {
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return TRUE;
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} else {
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return FALSE;
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}
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}
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/*
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Clean up Hw activity and errors
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Return status to Request's submitter and signal the event that tells
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it that the request is complete
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Clear up Sw context to allow new request to start
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@param[in] Context - driver context
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*/
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VOID
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FinishTransfer (
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I2C_MASTER_CONTEXT *Context
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)
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{
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UINT32 Attempts = 10000;
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MmioWrite32 ( Context->MmioAddress + R_IC_ENABLE, 0 );
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while ( MmioRead32 ( Context->MmioAddress + R_IC_ENABLE_STATUS ) & B_IC_EN ) {
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//try for 1ms; should take no more than 100us even at slowest bus speed, but just to make sure BIOS doesn't hang in infinite loop
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MicroSecondDelay ( 1 );
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if (--Attempts == 0) {
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ASSERT (FALSE);
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break;
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}
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}
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//
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//clear errors
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//
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MmioRead32 (Context->MmioAddress + R_IC_CLR_TX_ABRT);
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MmioRead32 (Context->MmioAddress + R_IC_CLR_INTR);
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//
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//clean up context data
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//
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Context->TransferInProgress = FALSE;
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}
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/**
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PerformTransfer. For synchronous transfer this function is called in a loop
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and for asynchronous transfers, as a timer callback. It writes data and/or
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read requests to hadrware, copies read data to destination buffers. When
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transfer completes, it cleans up Sw context and Hw registers in preparation
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for new transfer
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@param[in] Context - driver context
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**/
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VOID
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PerformTransfer (
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IN I2C_MASTER_CONTEXT *Context
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)
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{
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if (!Context->TransferInProgress) {
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return;
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}
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if (EFI_ERROR (Context->TransferStatus) || IsTransferFinished (Context)) {
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FinishTransfer (Context);
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return;
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}
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WriteFifo (Context);
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ReadFifo (Context);
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CheckErrors (Context);
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}
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/**
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Set the I2C controller bus clock frequency.
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This routine must be called at or below TPL_NOTIFY.
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The software and controller do a best case effort of using the specified
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frequency for the I2C bus. If the frequency does not match exactly then
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the controller will use lower frequency for the I2C to avoid exceeding
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the operating conditions for any of the I2C devices on the bus.
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For example if 400 KHz was specified and the controller's divide network
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only supports 402 KHz or 398 KHz then the controller would be set to 398
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KHz.
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@param[in] MmioAddress Address of I2C controller
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@param[in] BusClockHertz New I2C bus clock frequency in Hertz
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@retval EFI_SUCCESS The bus frequency was set successfully.
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@retval EFI_UNSUPPORTED The controller does not support this frequency.
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**/
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EFI_STATUS
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FrequencySet (
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IN UINTN MmioAddress,
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IN OUT UINTN *BusClockHertz
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)
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{
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UINT32 Speed;
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if ( *BusClockHertz < 100*1000) {
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//can't run that slowly
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return EFI_UNSUPPORTED;
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} else if ( *BusClockHertz < 400*1000) {
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//for any request in range [100kHz, 400kHz), set 100kHz
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*BusClockHertz = 100000;
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Speed = V_IC_SPEED_STANDARD;
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MmioWrite32 ( MmioAddress + R_IC_SDA_HOLD, 0x001C001C);
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MmioWrite32 ( MmioAddress + R_IC_SS_SCL_HCNT, 528);
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MmioWrite32 ( MmioAddress + R_IC_SS_SCL_LCNT, 640);
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} else if ( *BusClockHertz < 1000*1000) {
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//for any request in range [400kHz, 1MHz), set 400kHz
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*BusClockHertz = 400000;
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Speed = V_IC_SPEED_FAST;
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MmioWrite32 ( MmioAddress + R_IC_SDA_HOLD, 0x001C001C);
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MmioWrite32 ( MmioAddress + R_IC_FS_SCL_HCNT, 128);
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MmioWrite32 ( MmioAddress + R_IC_FS_SCL_LCNT, 160);
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} else {
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//for any request in range [1MHz, +inf), set 1MHz. This silicon doesn't support 3.4MHz mode.
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*BusClockHertz = 1000000;
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Speed = V_IC_SPEED_FAST;
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MmioWrite32 ( MmioAddress + R_IC_SDA_HOLD, 0x00280028);
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MmioWrite32 ( MmioAddress + R_IC_FS_SCL_HCNT, 30);
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MmioWrite32 ( MmioAddress + R_IC_FS_SCL_LCNT, 80);
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}
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MmioWrite32 ( MmioAddress + R_IC_CON, Speed | B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_IC_MASTER_MODE);
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return EFI_SUCCESS;
|
}
|
|
|
/**
|
Reset the I2C controller
|
|
@param[in] MmioAddress Address of I2C controller
|
|
@retval Status
|
**/
|
EFI_STATUS
|
I2cReset (
|
IN UINTN MmioAddress
|
)
|
{
|
MmioAnd32 (
|
MmioAddress + R_PCH_SERIAL_IO_PPR_RESETS,
|
(UINT32) ~(B_PCH_SERIAL_IO_PPR_RESETS_FUNC | B_PCH_SERIAL_IO_PPR_RESETS_APB | B_PCH_SERIAL_IO_PPR_RESETS_IDMA)
|
);
|
MmioRead32 (MmioAddress + R_PCH_SERIAL_IO_PPR_RESETS);
|
MmioOr32 (
|
MmioAddress + R_PCH_SERIAL_IO_PPR_RESETS,
|
B_PCH_SERIAL_IO_PPR_RESETS_FUNC | B_PCH_SERIAL_IO_PPR_RESETS_APB | B_PCH_SERIAL_IO_PPR_RESETS_IDMA
|
);
|
MmioRead32 (MmioAddress + R_PCH_SERIAL_IO_PPR_RESETS);
|
|
return EFI_SUCCESS;
|
}
|
|
|
