/** @file
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PCH SPI PEI Library implements the SPI Host Controller Interface.
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include <PchReservedResources.h>
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#include <IndustryStandard/Pci30.h>
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#include <Ppi/Spi.h>
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#include <Register/PchRegsLpc.h>
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#include <Register/PchRegsSpi.h>
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#include <Library/DebugLib.h>
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#include <Library/IoLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PchCycleDecodingLib.h>
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#include <Library/PchSpiCommonLib.h>
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#include <Library/PciSegmentLib.h>
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#include <Library/PeiServicesLib.h>
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typedef struct {
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EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
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SPI_INSTANCE SpiInstance;
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} PEI_SPI_INSTANCE;
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/**
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Initializes the SPI BAR0 value to a default value and enables memory space decoding.
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The SPI BAR0 will be assigned later in PCI enumeration.
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**/
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VOID
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InitSpiBar0 (
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VOID
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)
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{
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UINT64 PchSpiBase;
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PchSpiBase = PCI_SEGMENT_LIB_ADDRESS (
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0,
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0,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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PciSegmentWrite32 (PchSpiBase + R_PCH_SPI_BAR0, PCH_SPI_BASE_ADDRESS);
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PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
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}
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/**
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Initializes SPI for access from future services.
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@retval EFI_SUCCESS The SPI service was initialized successfully.
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@retval EFI_OUT_OF_RESOUCES Insufficient memory available to allocate structures required for initialization.
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@retval Others An error occurred initializing SPI services.
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**/
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EFI_STATUS
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EFIAPI
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SpiServiceInit (
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VOID
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)
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{
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EFI_STATUS Status;
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PEI_SPI_INSTANCE *PeiSpiInstance;
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SPI_INSTANCE *SpiInstance;
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PCH_SPI_PPI *SpiPpi;
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UINT16 AcpiBase;
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AcpiBase = 0;
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Status = PeiServicesLocatePpi (
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&gPchSpiPpiGuid,
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0,
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NULL,
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(VOID **) &SpiPpi
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);
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if (Status != EFI_SUCCESS) {
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//
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// Initialize the ACPI base address so the ACPI PM timer can be used to wait for
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// SPI cycle completion
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//
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PchAcpiBaseGet (&AcpiBase);
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if (AcpiBase == 0) {
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PchAcpiBaseSet (PcdGet16 (PcdAcpiBaseAddress));
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}
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//
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// Prior to PCI enumeration, initialize SPI BAR0 to a default value
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// and also enable memory space decoding for SPI
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//
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InitSpiBar0 ();
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PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE));
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if (NULL == PeiSpiInstance) {
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return EFI_OUT_OF_RESOURCES;
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}
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SpiInstance = &(PeiSpiInstance->SpiInstance);
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SpiProtocolConstructor (SpiInstance);
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PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
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PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid;
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PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol);
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Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor);
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}
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return Status;
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}
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/**
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Acquires the PCH SPI BAR0 MMIO address.
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@param[in] SpiInstance Pointer to SpiInstance to initialize
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@retval UINTN The SPIO BAR0 MMIO address
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**/
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UINTN
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AcquireSpiBar0 (
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IN SPI_INSTANCE *SpiInstance
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)
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{
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return MmioRead32 (SpiInstance->PchSpiBase + R_PCH_SPI_BAR0) & ~(B_PCH_SPI_BAR0_MASK);
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}
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/**
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Release the PCH SPI BAR0 MMIO address.
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@param[in] SpiInstance Pointer to SpiInstance to initialize
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@retval None
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**/
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VOID
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ReleaseSpiBar0 (
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IN SPI_INSTANCE *SpiInstance
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)
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{
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return;
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}
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/**
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Disables BIOS Write Protect
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@retval EFI_SUCCESS BIOS Write Protect was disabled successfully
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**/
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EFI_STATUS
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EFIAPI
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DisableBiosWriteProtect (
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VOID
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)
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{
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UINT64 SpiBaseAddress;
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SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
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0,
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0,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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//
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// Clear EISS bit to allow for SPI use
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//
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PciSegmentAnd8 (SpiBaseAddress + R_PCH_SPI_BC, (UINT8) ~B_PCH_SPI_BC_EISS);
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//
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// Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
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//
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PciSegmentOr8 (
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SpiBaseAddress + R_PCH_SPI_BC + 1,
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(B_PCH_SPI_BC_SYNC_SS >> 8)
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);
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//
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// Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
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// Enable the access to the BIOS space for both read and write cycles
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//
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PciSegmentOr8 (
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SpiBaseAddress + R_PCH_SPI_BC,
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B_PCH_SPI_BC_WPD
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);
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ASSERT ((PciSegmentRead8 (SpiBaseAddress + R_PCH_SPI_BC) & B_PCH_SPI_BC_EISS) == 0);
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return EFI_SUCCESS;
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}
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/**
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Enables BIOS Write Protect
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**/
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VOID
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EFIAPI
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EnableBiosWriteProtect (
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VOID
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)
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{
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UINT64 SpiBaseAddress;
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SpiBaseAddress = PCI_SEGMENT_LIB_ADDRESS (
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0,
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0,
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PCI_DEVICE_NUMBER_PCH_SPI,
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PCI_FUNCTION_NUMBER_PCH_SPI,
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0
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);
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//
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// Disable the access to the BIOS space for write cycles
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//
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PciSegmentAnd8 (
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SpiBaseAddress + R_PCH_SPI_BC,
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(UINT8) (~B_PCH_SPI_BC_WPD)
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);
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}
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