/** @file
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This file is to load sample board policy.
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Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyLibrary.h"
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#include <Library/ConfigBlockLib.h>
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/*
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Apply sample board PCH specific default settings
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@param[in] SiPolicy The pointer to SI Policy PPI instance
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*/
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VOID
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EFIAPI
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PchLoadSamplePolicy (
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IN SI_POLICY_PPI *SiPolicy
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)
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{
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UINTN Index;
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EFI_STATUS Status;
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PCH_PCIE_CONFIG *PcieRpConfig;
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PCH_IOAPIC_CONFIG *IoApicConfig;
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PCH_CIO2_CONFIG *Cio2Config;
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PCH_DMI_CONFIG *DmiConfig;
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PCH_LAN_CONFIG *LanConfig;
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PCH_LOCK_DOWN_CONFIG *LockDownConfig;
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PCH_PM_CONFIG *PmConfig;
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PCH_SCS_CONFIG *ScsConfig;
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PCH_SERIAL_IO_CONFIG *SerialIoConfig;
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PCH_THERMAL_CONFIG *ThermalConfig;
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PCH_USB_CONFIG *UsbConfig;
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gCio2ConfigGuid, (VOID *) &Cio2Config);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &ThermalConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
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ASSERT_EFI_ERROR (Status);
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//
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// PCIE RP
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//
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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PcieRpConfig->RootPort[Index].ClkReqDetect = TRUE;
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PcieRpConfig->RootPort[Index].AdvancedErrorReporting = TRUE;
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PcieRpConfig->RootPort[Index].Gen3EqPh3Method = PchPcieEqSoftware;
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}
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PcieRpConfig->RootPort[0].ClkReqSupported = TRUE;
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PcieRpConfig->RootPort[0].ClkReqNumber = 2;
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PcieRpConfig->RootPort[4].ClkReqSupported = TRUE;
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PcieRpConfig->RootPort[4].ClkReqNumber = 3;
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PcieRpConfig->RootPort[5].ClkReqSupported = TRUE;
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PcieRpConfig->RootPort[5].ClkReqNumber = 1;
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PcieRpConfig->RootPort[8].ClkReqSupported = TRUE;
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PcieRpConfig->RootPort[8].ClkReqNumber = 5;
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PcieRpConfig->RootPort[9].ClkReqSupported = TRUE;
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PcieRpConfig->RootPort[9].ClkReqNumber = 4;
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//
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// USB
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//
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UsbConfig->PortUsb20[0].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[0].Afe.Txiset = 0;
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UsbConfig->PortUsb20[0].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[0].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[1].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[1].Afe.Txiset = 0;
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UsbConfig->PortUsb20[1].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[1].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[2].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[2].Afe.Txiset = 0;
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UsbConfig->PortUsb20[2].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[2].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[3].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[3].Afe.Txiset = 0;
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UsbConfig->PortUsb20[3].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[3].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[4].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[4].Afe.Txiset = 0;
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UsbConfig->PortUsb20[4].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[4].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[5].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[5].Afe.Txiset = 0;
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UsbConfig->PortUsb20[5].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[5].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[6].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[6].Afe.Txiset = 0;
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UsbConfig->PortUsb20[6].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[6].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[7].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[7].Afe.Txiset = 0;
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UsbConfig->PortUsb20[7].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[7].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[8].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[8].Afe.Txiset = 5;
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UsbConfig->PortUsb20[8].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[8].Afe.Pehalfbit = 1;
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UsbConfig->PortUsb20[9].Afe.Petxiset = 7;
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UsbConfig->PortUsb20[9].Afe.Txiset = 0;
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UsbConfig->PortUsb20[9].Afe.Predeemp = 2;
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UsbConfig->PortUsb20[9].Afe.Pehalfbit = 1;
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// OC Map for USB2 Ports
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UsbConfig->PortUsb20[ 0].OverCurrentPin = PchUsbOverCurrentPin0;
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UsbConfig->PortUsb20[ 1].OverCurrentPin = PchUsbOverCurrentPin2;
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UsbConfig->PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2;
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UsbConfig->PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin1;
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UsbConfig->PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPinSkip;
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// OC Map for USB3 Ports
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UsbConfig->PortUsb30[0].OverCurrentPin = PchUsbOverCurrentPin0;
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UsbConfig->PortUsb30[1].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1;
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UsbConfig->PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPinSkip;
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UsbConfig->SsicConfig.SsicPort[0].Enable = TRUE;
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UsbConfig->SsicConfig.SsicPort[1].Enable = TRUE;
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//
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// IOAPIC
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//
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IoApicConfig->BdfValid = 1;
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IoApicConfig->BusNumber = 0xF0;
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IoApicConfig->DeviceNumber = 0x1F;
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IoApicConfig->FunctionNumber = 0;
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//
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// LAN
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//
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LanConfig->K1OffEnable = TRUE;
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LanConfig->ClkReqSupported = TRUE;
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LanConfig->ClkReqNumber = 3;
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//
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// PM CONFIG
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//
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PmConfig->LpcClockRun = TRUE;
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//
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// DMI
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//
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DmiConfig->PwrOptEnable = TRUE;
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//
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// SERIALIO
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//
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SerialIoConfig->DevMode[PchSerialIoIndexI2C0] = PchSerialIoPci;
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SerialIoConfig->DevMode[PchSerialIoIndexI2C1] = PchSerialIoPci;
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SerialIoConfig->DevMode[PchSerialIoIndexI2C2] = PchSerialIoDisabled;
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SerialIoConfig->DevMode[PchSerialIoIndexI2C3] = PchSerialIoDisabled;
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SerialIoConfig->DevMode[PchSerialIoIndexI2C4] = PchSerialIoAcpiHidden;
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SerialIoConfig->DevMode[PchSerialIoIndexI2C5] = PchSerialIoDisabled;
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SerialIoConfig->DevMode[PchSerialIoIndexSpi0] = PchSerialIoDisabled;
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SerialIoConfig->DevMode[PchSerialIoIndexSpi1] = PchSerialIoDisabled;
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SerialIoConfig->DevMode[PchSerialIoIndexUart0] = PchSerialIoPci;
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SerialIoConfig->DevMode[PchSerialIoIndexUart1] = PchSerialIoDisabled;
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SerialIoConfig->DevMode[PchSerialIoIndexUart2] = PchSerialIoLegacyUart;
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SerialIoConfig->I2cVoltage[2] = 1;
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SerialIoConfig->I2cVoltage[3] = 1;
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SerialIoConfig->SpiCsPolarity[0] = 1;
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SerialIoConfig->UartHwFlowCtrl[0] = 1;
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SerialIoConfig->UartHwFlowCtrl[1] = 1;
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SerialIoConfig->UartHwFlowCtrl[2] = 1;
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//
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// SCS
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//
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ScsConfig->ScsEmmcHs400Enabled = TRUE;
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ScsConfig->ScsEmmcHs400TuningRequired = TRUE;
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}
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