/** @file
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Print whole PCH_PREMEM_POLICY_PPI
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Copyright (c) 2017 - 2020 Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "PeiPchPolicyLibrary.h"
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#include <Library/ConfigBlockLib.h>
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/**
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Print PCH_GENERAL_PREMEM_CONFIG and serial out.
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@param[in] PchGeneralPreMemConfig Pointer to a PCH_GENERAL_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintGeneralPreMemConfig (
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IN CONST PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ PCH General PreMem Config -----------\n"));
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DEBUG ((DEBUG_INFO, " AcpiBase= %x\n", PchGeneralPreMemConfig->AcpiBase));
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DEBUG ((DEBUG_INFO, " Port80Route= %x\n", PchGeneralPreMemConfig->Port80Route));
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}
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/**
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Print PCH_DCI_PREMEM_CONFIG and serial out.
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@param[in] DciPreMemConfig Pointer to a PCH_DCI_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintDciPreMemConfig (
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IN CONST PCH_DCI_PREMEM_CONFIG *DciPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ PCH DCI PreMem Config ---------------\n"));
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DEBUG ((DEBUG_INFO, "DciEn= %x\n", DciPreMemConfig->DciEn));
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}
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/**
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Print PCH_WDT_PREMEM_CONFIG and serial out.
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@param[in] WdtPreMemConfig Pointer to a PCH_WDT_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintWdtPreMemConfig (
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IN CONST PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ PCH WDT PreMem Config ---------------\n"));
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DEBUG ((DEBUG_INFO, "DisableAndLock= %x\n", WdtPreMemConfig->DisableAndLock));
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}
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/**
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Print PCH_TRACE_HUB_CONFIG and serial out.
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@param[in] TraceHubConfig Pointer to a PCH_TRACE_HUB_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintTraceHubPreMemConfig (
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IN CONST PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ PCH TraceHub PreMem Config ----------\n"));
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DEBUG ((DEBUG_INFO, "EnableMode= %x\n", TraceHubPreMemConfig->EnableMode));
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DEBUG ((DEBUG_INFO, "MemReg0Size= %x\n", TraceHubPreMemConfig->MemReg0Size));
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DEBUG ((DEBUG_INFO, "MemReg1Size= %x\n", TraceHubPreMemConfig->MemReg1Size));
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}
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/**
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Print PCH_HPET_PREMEM_CONFIG and serial out.
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@param[in] HpetPreMemConfig Pointer to a PCH_HPET_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintHpetPreMemConfig (
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IN CONST PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ PCH HPET PreMem Config --------------\n"));
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DEBUG ((DEBUG_INFO, " Enable %x\n", HpetPreMemConfig->Enable));
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DEBUG ((DEBUG_INFO, " BdfValid %x\n", HpetPreMemConfig->BdfValid));
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DEBUG ((DEBUG_INFO, " BusNumber %x\n", HpetPreMemConfig->BusNumber));
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DEBUG ((DEBUG_INFO, " DeviceNumber %x\n", HpetPreMemConfig->DeviceNumber));
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DEBUG ((DEBUG_INFO, " FunctionNumber %x\n", HpetPreMemConfig->FunctionNumber));
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DEBUG ((DEBUG_INFO, " Base %x\n", HpetPreMemConfig->Base));
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}
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/**
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Print PCH_SMBUS_CONFIG and serial out.
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@param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintSmbusPreMemConfig (
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IN CONST PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig
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)
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{
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UINT32 Index;
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DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS PreMem Config -------------\n"));
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DEBUG ((DEBUG_INFO, " Enable= %x\n", SmbusPreMemConfig->Enable));
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DEBUG ((DEBUG_INFO, " ArpEnable= %x\n", SmbusPreMemConfig->ArpEnable));
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DEBUG ((DEBUG_INFO, " DynamicPowerGating= %x\n", SmbusPreMemConfig->DynamicPowerGating));
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DEBUG ((DEBUG_INFO, " SpdWriteDisable= %x\n", SmbusPreMemConfig->SpdWriteDisable));
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DEBUG ((DEBUG_INFO, " SmbusIoBase= %x\n", SmbusPreMemConfig->SmbusIoBase));
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DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses= %x\n", SmbusPreMemConfig->NumRsvdSmbusAddresses));
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DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable= {"));
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for (Index = 0; Index < SmbusPreMemConfig->NumRsvdSmbusAddresses; ++Index) {
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DEBUG ((DEBUG_INFO, " %02xh", SmbusPreMemConfig->RsvdSmbusAddressTable[Index]));
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}
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DEBUG ((DEBUG_INFO, " }\n"));
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}
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/**
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Print PCH_LPC_PREMEM_CONFIG and serial out.
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@param[in] LpcPreMemConfig Pointer to a PCH_LPC_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintLpcPreMemConfig (
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IN CONST PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ PCH LPC PreMem Config ---------------\n"));
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DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding= %x\n", LpcPreMemConfig->EnhancePort8xhDecoding));
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}
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/**
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Print PCH_HSIO_PCIE_PREMEM_CONFIG and serial out.
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@param[in] HsioPciePreMemConfig Pointer to a PCH_HSIO_PCIE_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintHsioPciePreMemConfig (
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IN CONST PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig
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)
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{
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UINT32 Index;
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DEBUG ((DEBUG_INFO, "------------------ HSIO PCIE PreMem Config -------------\n"));
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DEBUG ((DEBUG_INFO, " PciePllSsc = %x\n", HsioPciePreMemConfig->PciePllSsc));
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioRxSetCtleEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioRxSetCtle= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen3DownscaleAmpEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen3DownscaleAmp= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DeEmphEnable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen1DeEmph= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph3p5Enable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph3p5= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph6p0Enable= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable));
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DEBUG ((DEBUG_INFO, " Rp[%d] HsioTxGen2DeEmph6p0= %x\n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0));
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}
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}
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/**
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Print PCH_HSIO_SATA_PREMEM_CONFIG and serial out.
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@param[in] HsioSataPreMemConfig Pointer to a PCH_HSIO_SATA_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintHsioSataPreMemConfig (
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IN CONST PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig
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)
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{
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UINT32 Index;
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DEBUG ((DEBUG_INFO, "------------------ HSIO SATA PreMem Config -------------\n"));
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for (Index = 0; Index < GetPchMaxSataPortNum (); Index++) {
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable));
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DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph));
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}
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}
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/**
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Print PCH_HSIO_PREMEM_CONFIG and serial out.
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@param[in] HsioPreMemConfig Pointer to a PCH_HSIO_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintHsioPreMemConfig (
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IN CONST PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig
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)
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{
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DEBUG ((DEBUG_INFO, "------------------ HSIO PreMem Config ------------------\n"));
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DEBUG ((DEBUG_INFO, " ChipsetInitMessage : 0x%x\n", HsioPreMemConfig->ChipsetInitMessage));
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DEBUG ((DEBUG_INFO, " BypassPhySyncReset : 0x%x\n", HsioPreMemConfig->BypassPhySyncReset));
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}
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/**
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Print PCH_PCIE_RP_PREMEM_CONFIG and serial out.
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@param[in] PcieRpPreMemConfig Pointer to a PCH_PCIE_RP_PREMEM_CONFIG that provides the platform setting
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**/
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VOID
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PchPrintPcieRpPreMemConfig (
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IN CONST PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig
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)
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{
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UINT32 Index;
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DEBUG ((DEBUG_INFO, "------------------ PCH PCIe RP PreMem Config -----------\n"));
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for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) {
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DEBUG ((DEBUG_INFO, " Port[%d] RpEnabled= %x\n", Index, (PcieRpPreMemConfig->RpEnabledMask & (UINT32) (1 << Index)) != 0 ));
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}
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}
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/**
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Print whole PCH_POLICY_PPI and serial out.
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@param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
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**/
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VOID
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PchPreMemPrintPolicyPpi (
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IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
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)
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{
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DEBUG_CODE_BEGIN ();
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EFI_STATUS Status;
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PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
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PCH_DCI_PREMEM_CONFIG *DciPreMemConfig;
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PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig;
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PCH_TRACE_HUB_PREMEM_CONFIG *TraceHubPreMemConfig;
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PCH_HPET_PREMEM_CONFIG *HpetPreMemConfig;
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PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig;
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PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig;
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PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig;
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PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig;
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PCH_HSIO_PREMEM_CONFIG *HsioPreMemConfig;
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PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gDciPreMemConfigGuid, (VOID *) &DciPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gWatchDogPreMemConfigGuid, (VOID *) &WdtPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gTraceHubPreMemConfigGuid, (VOID *) &TraceHubPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHpetPreMemConfigGuid, (VOID *) &HpetPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSmbusPreMemConfigGuid, (VOID *) &SmbusPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gLpcPreMemConfigGuid, (VOID *) &LpcPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioPciePreMemConfigGuid, (VOID *) &HsioPciePreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioSataPreMemConfigGuid, (VOID *) &HsioSataPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioPreMemConfigGuid, (VOID *) &HsioPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
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ASSERT_EFI_ERROR (Status);
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DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy Start ------------------------\n"));
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DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPreMemPolicyPpi->TableHeader.Header.Revision));
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PchPrintGeneralPreMemConfig (PchGeneralPreMemConfig);
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PchPrintDciPreMemConfig (DciPreMemConfig);
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PchPrintWdtPreMemConfig (WdtPreMemConfig);
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PchPrintTraceHubPreMemConfig (TraceHubPreMemConfig);
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PchPrintHpetPreMemConfig (HpetPreMemConfig);
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PchPrintSmbusPreMemConfig (SmbusPreMemConfig);
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PchPrintLpcPreMemConfig (LpcPreMemConfig);
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PchPrintHsioPciePreMemConfig (HsioPciePreMemConfig);
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PchPrintHsioSataPreMemConfig (HsioSataPreMemConfig);
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PchPrintHsioPreMemConfig (HsioPreMemConfig);
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PchPrintPcieRpPreMemConfig (PcieRpPreMemConfig);
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DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy End --------------------------\n"));
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DEBUG_CODE_END ();
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}
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