/** @file
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This file contains routines for GPIO initialization
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#include "GpioLibrary.h"
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/**
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This procedure will handle requirement on gSPIx_CSB pins.
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@param[in] GpioPad GPIO pad
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@param[in] PadMode GPIO PadMode value
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@param[in out] Dw0Reg Value for PADCFG_DW0 register
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@param[in out] Dw0RegMask Mask of bits which will change in PADCFG_DWO register
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@retval None
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**/
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STATIC
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VOID
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GpioHandleGSpiCSBPad (
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IN GPIO_PAD GpioPad,
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IN UINT32 PadMode,
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IN OUT UINT32 *Dw0Reg,
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IN OUT UINT32 *Dw0RegMask
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)
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{
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//
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// For gSPIx_CSB pins if are going to be used in native mode then skip setting
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// pad mode here.
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//
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if (GpioIsGpioPadAGSpiCsbPin (GpioPad, PadMode)) {
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//
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// Skip setting PadMode to native, leave it in GPIO mode.
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// Setting it to native should be done after Serial IO initialization
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//
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*Dw0RegMask |= B_PCH_GPIO_PAD_MODE;
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*Dw0Reg &= ~B_PCH_GPIO_PAD_MODE;
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*Dw0Reg |= ((GpioPadModeGpio >> 1) << N_PCH_GPIO_PAD_MODE);
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}
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}
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/**
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This procedure will handle requirement on SATA DEVSLPx pins.
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@param[in] GpioPad GPIO pad
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@param[in] PadMode GPIO PadMode value
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@param[in out] Dw0Reg Value for PADCFG_DW0 register
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@param[in out] Dw0RegMask Mask of bits which will change in PADCFG_DWO register
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@retval None
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**/
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STATIC
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VOID
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GpioHandleSataDevSlpPad (
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IN GPIO_PAD GpioPad,
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IN UINT32 PadMode,
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IN OUT UINT32 *Dw0Reg,
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IN OUT UINT32 *Dw0RegMask
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)
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{
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//
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// For SATA DEVSLPx pins if used in native 1 mode then ensure that PadRstCfg
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// is set to "00" - Powergood
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//
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if (GpioIsPadASataDevSlpPin (GpioPad, PadMode)) {
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//
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// Set PadRstCfg to Powergood
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//
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*Dw0RegMask |= B_PCH_GPIO_RST_CONF;
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*Dw0Reg &= ~B_PCH_GPIO_RST_CONF;
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*Dw0Reg |= ((GpioResumeReset >> 1) << N_PCH_GPIO_RST_CONF);
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}
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}
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//
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// GPIO_DW_REG_VALUE structure is used by GpioConfigureSklPch function
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// to cache values which will be programmed into respective GPIO registers
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// after all GpioPads are processed. This way MMIO accesses are decreased
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// and instead of doing one programming for one GpioPad there is only
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// one access for whole register.
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//
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typedef struct {
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UINT32 HostSoftOwnReg;
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UINT32 HostSoftOwnRegMask;
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UINT32 GpiGpeEnReg;
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UINT32 GpiGpeEnRegMask;
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UINT32 GpiNmiEnReg;
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UINT32 GpiNmiEnRegMask;
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UINT32 PadsToLock;
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UINT32 PadsToLockTx;
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} GPIO_DW_REG_VALUE;
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//
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// GPIO_DW_REG_NUMBER contains number of DWords required to
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// store Pad data for all groups. Each pad uses one bit.
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//
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// For Skylake and Kabylake each group has <32 pads what
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// makes GPIO_DW_REG_NUMBER = 1
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//
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#define GPIO_DW_REG_NUMBER 1
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/**
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Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
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@param[in] PadNumber GPIO pad number
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@param[in] GpioConfig GPIO Config data
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@param[in out] DwRegsValues Values for GPIO DW Registers
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@retval None
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**/
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STATIC
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VOID
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GpioDwRegValueFromGpioConfig (
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IN UINT32 PadNumber,
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IN GPIO_CONFIG *GpioConfig,
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IN OUT GPIO_DW_REG_VALUE *DwRegsValues
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)
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{
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UINT32 PadBitPosition;
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UINT32 DwNum;
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PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
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DwNum = GPIO_GET_DW_NUM (PadNumber);
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if (DwNum >= GPIO_DW_REG_NUMBER) {
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ASSERT (FALSE);
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return;
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}
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//
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// Update value to be programmed in HOSTSW_OWN register
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//
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DwRegsValues[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
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DwRegsValues[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
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//
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// Update value to be programmed in GPI_GPE_EN register
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//
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DwRegsValues[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
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DwRegsValues[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
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//
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// Update value to be programmed in GPI_NMI_EN register
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//
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DwRegsValues[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
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DwRegsValues[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
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//
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// Update information on Pad Configuration Lock
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//
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DwRegsValues[DwNum].PadsToLock |= ((GpioConfig->LockConfig >> 0x1) & 0x1) << PadBitPosition;
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//
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// Update information on Pad Configuration Lock Tx
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//
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DwRegsValues[DwNum].PadsToLockTx |= ((GpioConfig->LockConfig >> 0x2) & 0x1) << PadBitPosition;
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}
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/**
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This SKL PCH specific procedure will initialize multiple SKL PCH GPIO pins
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@param[in] NumberofItem Number of GPIO pads to be updated
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@param[in] GpioInitTableAddress GPIO initialization table
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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STATIC
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EFI_STATUS
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GpioConfigureSklPch (
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IN UINT32 NumberOfItems,
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IN GPIO_INIT_CONFIG *GpioInitTableAddress
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)
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{
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UINT32 Index;
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UINT32 PadCfgDwReg[2];
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UINT32 PadCfgDwRegMask[2];
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UINT32 PadCfgReg;
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GPIO_DW_REG_VALUE DwRegsValues[GPIO_DW_REG_NUMBER];
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UINT32 DwNum;
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GPIO_GROUP_INFO *GpioGroupInfo;
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UINTN GpioGroupInfoLength;
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GPIO_GROUP GpioGroupOffset;
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UINT32 NumberOfGroups;
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GPIO_PAD_OWN PadOwnVal;
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GPIO_INIT_CONFIG *GpioData;
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GPIO_GROUP Group;
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UINT32 GroupIndex;
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UINT32 PadNumber;
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PCH_SERIES PchSeries;
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PchSeries = GetPchSeries ();
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PadOwnVal = GpioPadOwnHost;
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GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
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GpioGroupOffset = GpioGetLowestGroup ();
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NumberOfGroups = GpioGetNumberOfGroups ();
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Index = 0;
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while (Index < NumberOfItems) {
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GpioData = &GpioInitTableAddress[Index];
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Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
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GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
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PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
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if (GroupIndex >= V_PCH_GPIO_GROUP_MAX) {
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// @todo SKL PCH: one platform code ready we should add this back ASSERT (FALSE);
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continue;
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}
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DEBUG_CODE_BEGIN ();
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if (!(((PchSeries == PchH) && (GPIO_GET_CHIPSET_ID (GpioData->GpioPad) == GPIO_SKL_H_CHIPSET_ID)) ||
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((PchSeries == PchLp) && (GPIO_GET_CHIPSET_ID (GpioData->GpioPad) == GPIO_SKL_LP_CHIPSET_ID)))) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad define used on this chipset (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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ASSERT (FALSE);
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return EFI_UNSUPPORTED;
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}
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DEBUG_CODE_END ();
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//
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// Check if group argument exceeds GPIO group range
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//
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if ((Group < GpioGroupOffset) || (Group >= NumberOfGroups + GpioGroupOffset)) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Invalid group %d\n", GroupIndex));
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return EFI_INVALID_PARAMETER;
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}
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ZeroMem (DwRegsValues, sizeof (DwRegsValues));
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//
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// Loop through pads for one group. If pad belongs to a different group then
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// break and move to register programming.
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//
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while (Index < NumberOfItems) {
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GpioData = &GpioInitTableAddress[Index];
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if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
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//if next pad is from different group then break loop
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break;
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}
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PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
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//
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// Check if legal pin number
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//
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if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
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return EFI_INVALID_PARAMETER;
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}
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DEBUG_CODE_BEGIN ();
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//
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// Check if selected GPIO Pad is not owned by CSME/ISH
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//
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GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
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if (PadOwnVal != GpioPadOwnHost) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
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DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
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DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
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//Move to next item
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Index++;
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continue;
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}
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DEBUG_CODE_END ();
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ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
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ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
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//
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// Get GPIO PADCFG register value from GPIO config data
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//
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GpioPadCfgRegValueFromGpioConfig (
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GpioData->GpioPad,
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&GpioData->GpioConfig,
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PadCfgDwReg,
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PadCfgDwRegMask
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);
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//
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// Check for additional requirements on setting PADCFG register
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//
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GpioHandleGSpiCSBPad (GpioData->GpioPad, GpioData->GpioConfig.PadMode, &PadCfgDwReg[0], &PadCfgDwRegMask[0]);
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GpioHandleSataDevSlpPad (GpioData->GpioPad, GpioData->GpioConfig.PadMode, &PadCfgDwReg[0], &PadCfgDwRegMask[0]);
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//
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// Create PADCFG register offset using group and pad number
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//
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PadCfgReg = PAD_CFG_SIZE * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset;
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//
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// Write PADCFG DW0 register
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//
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg),
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~PadCfgDwRegMask[0],
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PadCfgDwReg[0]
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);
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//
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// Write PADCFG DW1 register
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//
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4),
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~PadCfgDwRegMask[1],
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PadCfgDwReg[1]
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);
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//
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// Get GPIO DW register values from GPIO config data
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//
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GpioDwRegValueFromGpioConfig (
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PadNumber,
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&GpioData->GpioConfig,
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DwRegsValues
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);
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//Move to next item
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Index++;
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}
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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//
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// Write HOSTSW_OWN registers
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//
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if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4),
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~DwRegsValues[DwNum].HostSoftOwnRegMask,
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DwRegsValues[DwNum].HostSoftOwnReg
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);
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}
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//
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// Write GPI_GPE_EN registers
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//
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if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4),
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~DwRegsValues[DwNum].GpiGpeEnRegMask,
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DwRegsValues[DwNum].GpiGpeEnReg
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);
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}
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//
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// Write GPI_NMI_EN registers
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//
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if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
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MmioAndThenOr32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4),
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~DwRegsValues[DwNum].GpiNmiEnRegMask,
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DwRegsValues[DwNum].GpiNmiEnReg
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);
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} else if (DwRegsValues[DwNum].GpiNmiEnReg != 0x0) {
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DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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}
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//
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// Write Pad Configuration Lock
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//
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if (DwRegsValues[DwNum].PadsToLock != 0) {
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GpioLockPadCfgForGroupDw (GroupIndex + GpioGroupOffset, DwNum, DwRegsValues[DwNum].PadsToLock);
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}
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//
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// Write Pad Configuration Lock Tx
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//
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if (DwRegsValues[DwNum].PadsToLockTx != 0) {
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GpioLockPadCfgTxForGroupDw (GroupIndex + GpioGroupOffset, DwNum, DwRegsValues[DwNum].PadsToLockTx);
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}
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}
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}
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return EFI_SUCCESS;
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}
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/**
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This procedure will clear all status bits of any GPIO interrupts.
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@param[in] none
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
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**/
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STATIC
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EFI_STATUS
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GpioClearAllGpioInterrupts (
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VOID
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)
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{
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GPIO_GROUP Group;
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GPIO_GROUP_INFO *GpioGroupInfo;
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GPIO_GROUP GpioGroupLowest;
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GPIO_GROUP GpioGroupHighest;
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UINT32 GroupIndex;
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UINTN GpioGroupInfoLength;
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UINT32 DwNum;
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GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
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GpioGroupLowest = GpioGetLowestGroup ();
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GpioGroupHighest = GpioGetHighestGroup ();
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for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
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GroupIndex = GpioGetGroupIndexFromGroup (Group);
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//
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// Check if group has GPI IS register
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//
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if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all GPI_IS Status bits by writing '1'
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//
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4),
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0xFFFFFFFF
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);
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}
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}
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//
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// Check if group has GPI_GPE_STS register
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//
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if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all GPI_GPE_STS Status bits by writing '1'
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//
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4),
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0xFFFFFFFF
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);
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}
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}
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//
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// Check if group has SMI_STS register
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//
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if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all SMI_STS Status bits by writing '1'
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//
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4),
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0xFFFFFFFF
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);
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}
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}
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//
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// Check if group has NMI_STS register
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//
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if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
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//
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// Clear all NMI_STS Status bits by writing '1'
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//
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for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
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MmioWrite32 (
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PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4),
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0xFFFFFFFF
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);
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}
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}
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}
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return EFI_SUCCESS;
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}
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|
/**
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This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
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Structure contains fields that can be used to configure each pad.
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Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
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Separate fields could be set to hardware default if it does not matter, except
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GpioPad and PadMode.
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Some GpioPads are configured and switched to native mode by RC, those include:
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SerialIo pins, ISH pins, ClkReq Pins
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@param[in] NumberofItem Number of GPIO pads to be updated
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@param[in] GpioInitTableAddress GPIO initialization table
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@retval EFI_SUCCESS The function completed successfully
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@retval EFI_INVALID_PARAMETER Invalid group or pad number
|
**/
|
EFI_STATUS
|
GpioConfigurePads (
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IN UINT32 NumberOfItems,
|
IN GPIO_INIT_CONFIG *GpioInitTableAddress
|
)
|
{
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EFI_STATUS Status;
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Status = GpioConfigureSklPch (NumberOfItems, GpioInitTableAddress);
|
GpioClearAllGpioInterrupts ();
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return Status;
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}
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|
