/**@file
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Define PCH NVS Area operatino region.
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//
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#ifndef _PCH_NVS_AREA_H_
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#define _PCH_NVS_AREA_H_
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#pragma pack (push,1)
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typedef struct {
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UINT16 PchSeries; ///< Offset 0 PCH Series
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UINT16 PchGeneration; ///< Offset 2 PCH Generation
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UINT32 RpAddress[24]; ///< Offset 4 Root Port address 1
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///< Offset 8 Root Port address 2
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///< Offset 12 Root Port address 3
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///< Offset 16 Root Port address 4
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///< Offset 20 Root Port address 5
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///< Offset 24 Root Port address 6
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///< Offset 28 Root Port address 7
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///< Offset 32 Root Port address 8
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///< Offset 36 Root Port address 9
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///< Offset 40 Root Port address 10
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///< Offset 44 Root Port address 11
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///< Offset 48 Root Port address 12
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///< Offset 52 Root Port address 13
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///< Offset 56 Root Port address 14
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///< Offset 60 Root Port address 15
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///< Offset 64 Root Port address 16
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///< Offset 68 Root Port address 17
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///< Offset 72 Root Port address 18
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///< Offset 76 Root Port address 19
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///< Offset 80 Root Port address 20
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///< Offset 84 Root Port address 21
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///< Offset 88 Root Port address 22
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///< Offset 92 Root Port address 23
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///< Offset 96 Root Port address 24
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UINT64 NHLA; ///< Offset 100 HD-Audio NHLT ACPI address
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UINT32 NHLL; ///< Offset 108 HD-Audio NHLT ACPI length
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UINT32 ADFM; ///< Offset 112 HD-Audio DSP Feature Mask
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UINT32 SBRG; ///< Offset 116 SBREG_BAR
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UINT32 GPEM; ///< Offset 120 GPP_X to GPE_DWX mapping
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UINT32 GP2T[10]; ///< Offset 124 GPE 2-tier level edged enabled Gpio pads (Group Index 0)
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///< Offset 128 GPE 2-tier level edged enabled Gpio pads (Group Index 1)
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///< Offset 132 GPE 2-tier level edged enabled Gpio pads (Group Index 2)
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///< Offset 136 GPE 2-tier level edged enabled Gpio pads (Group Index 3)
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///< Offset 140 GPE 2-tier level edged enabled Gpio pads (Group Index 4)
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///< Offset 144 GPE 2-tier level edged enabled Gpio pads (Group Index 5)
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///< Offset 148 GPE 2-tier level edged enabled Gpio pads (Group Index 6)
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///< Offset 152 GPE 2-tier level edged enabled Gpio pads (Group Index 7)
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///< Offset 156 GPE 2-tier level edged enabled Gpio pads (Group Index 8)
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///< Offset 160 GPE 2-tier level edged enabled Gpio pads (Group Index 9)
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UINT16 PcieLtrMaxSnoopLatency[24]; ///< Offset 164 PCIE LTR max snoop Latency 1
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///< Offset 166 PCIE LTR max snoop Latency 2
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///< Offset 168 PCIE LTR max snoop Latency 3
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///< Offset 170 PCIE LTR max snoop Latency 4
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///< Offset 172 PCIE LTR max snoop Latency 5
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///< Offset 174 PCIE LTR max snoop Latency 6
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///< Offset 176 PCIE LTR max snoop Latency 7
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///< Offset 178 PCIE LTR max snoop Latency 8
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///< Offset 180 PCIE LTR max snoop Latency 9
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///< Offset 182 PCIE LTR max snoop Latency 10
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///< Offset 184 PCIE LTR max snoop Latency 11
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///< Offset 186 PCIE LTR max snoop Latency 12
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///< Offset 188 PCIE LTR max snoop Latency 13
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///< Offset 190 PCIE LTR max snoop Latency 14
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///< Offset 192 PCIE LTR max snoop Latency 15
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///< Offset 194 PCIE LTR max snoop Latency 16
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///< Offset 196 PCIE LTR max snoop Latency 17
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///< Offset 198 PCIE LTR max snoop Latency 18
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///< Offset 200 PCIE LTR max snoop Latency 19
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///< Offset 202 PCIE LTR max snoop Latency 20
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///< Offset 204 PCIE LTR max snoop Latency 21
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///< Offset 206 PCIE LTR max snoop Latency 22
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///< Offset 208 PCIE LTR max snoop Latency 23
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///< Offset 210 PCIE LTR max snoop Latency 24
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UINT16 PcieLtrMaxNoSnoopLatency[24]; ///< Offset 212 PCIE LTR max no snoop Latency 1
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///< Offset 214 PCIE LTR max no snoop Latency 2
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///< Offset 216 PCIE LTR max no snoop Latency 3
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///< Offset 218 PCIE LTR max no snoop Latency 4
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///< Offset 220 PCIE LTR max no snoop Latency 5
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///< Offset 222 PCIE LTR max no snoop Latency 6
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///< Offset 224 PCIE LTR max no snoop Latency 7
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///< Offset 226 PCIE LTR max no snoop Latency 8
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///< Offset 228 PCIE LTR max no snoop Latency 9
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///< Offset 230 PCIE LTR max no snoop Latency 10
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///< Offset 232 PCIE LTR max no snoop Latency 11
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///< Offset 234 PCIE LTR max no snoop Latency 12
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///< Offset 236 PCIE LTR max no snoop Latency 13
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///< Offset 238 PCIE LTR max no snoop Latency 14
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///< Offset 240 PCIE LTR max no snoop Latency 15
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///< Offset 242 PCIE LTR max no snoop Latency 16
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///< Offset 244 PCIE LTR max no snoop Latency 17
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///< Offset 246 PCIE LTR max no snoop Latency 18
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///< Offset 248 PCIE LTR max no snoop Latency 19
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///< Offset 250 PCIE LTR max no snoop Latency 20
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///< Offset 252 PCIE LTR max no snoop Latency 21
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///< Offset 254 PCIE LTR max no snoop Latency 22
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///< Offset 256 PCIE LTR max no snoop Latency 23
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///< Offset 258 PCIE LTR max no snoop Latency 24
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UINT32 SerialIoDebugUart0Bar0; ///< Offset 260 SerialIo Hidden UART0 BAR 0
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UINT32 SerialIoDebugUart1Bar0; ///< Offset 264 SerialIo Hidden UART1 BAR 0
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UINT8 XHPC; ///< Offset 268 Number of HighSpeed ports implemented in XHCI controller
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UINT8 XRPC; ///< Offset 269 Number of USBR ports implemented in XHCI controller
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UINT8 XSPC; ///< Offset 270 Number of SuperSpeed ports implemented in XHCI controller
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UINT8 XSPA; ///< Offset 271 Address of 1st SuperSpeed port
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UINT32 HPTB; ///< Offset 272 HPET base address
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UINT8 HPTE; ///< Offset 276 HPET enable
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//SerialIo block
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UINT8 SMD[11]; ///< Offset 277 SerialIo controller 0 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 278 SerialIo controller 1 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 279 SerialIo controller 2 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 280 SerialIo controller 3 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 281 SerialIo controller 4 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 282 SerialIo controller 5 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 283 SerialIo controller 6 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 284 SerialIo controller 7 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 285 SerialIo controller 8 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 286 SerialIo controller 9 mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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///< Offset 287 SerialIo controller A mode (0: disabled, 1: pci, 2: acpi, 3: debug port)
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UINT8 SIR[11]; ///< Offset 288 SerialIo controller 0 irq number
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///< Offset 289 SerialIo controller 1 irq number
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///< Offset 290 SerialIo controller 2 irq number
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///< Offset 291 SerialIo controller 3 irq number
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///< Offset 292 SerialIo controller 4 irq number
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///< Offset 293 SerialIo controller 5 irq number
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///< Offset 294 SerialIo controller 6 irq number
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///< Offset 295 SerialIo controller 7 irq number
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///< Offset 296 SerialIo controller 8 irq number
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///< Offset 297 SerialIo controller 9 irq number
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///< Offset 298 SerialIo controller A irq number
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UINT64 SB0[11]; ///< Offset 299 SerialIo controller 0 BAR0
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///< Offset 307 SerialIo controller 1 BAR0
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///< Offset 315 SerialIo controller 2 BAR0
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///< Offset 323 SerialIo controller 3 BAR0
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///< Offset 331 SerialIo controller 4 BAR0
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///< Offset 339 SerialIo controller 5 BAR0
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///< Offset 347 SerialIo controller 6 BAR0
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///< Offset 355 SerialIo controller 7 BAR0
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///< Offset 363 SerialIo controller 8 BAR0
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///< Offset 371 SerialIo controller 9 BAR0
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///< Offset 379 SerialIo controller A BAR0
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UINT64 SB1[11]; ///< Offset 387 SerialIo controller 0 BAR1
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///< Offset 395 SerialIo controller 1 BAR1
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///< Offset 403 SerialIo controller 2 BAR1
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///< Offset 411 SerialIo controller 3 BAR1
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///< Offset 419 SerialIo controller 4 BAR1
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///< Offset 427 SerialIo controller 5 BAR1
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///< Offset 435 SerialIo controller 6 BAR1
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///< Offset 443 SerialIo controller 7 BAR1
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///< Offset 451 SerialIo controller 8 BAR1
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///< Offset 459 SerialIo controller 9 BAR1
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///< Offset 467 SerialIo controller A BAR1
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//end of SerialIo block
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UINT8 GPEN; ///< Offset 475 GPIO enabled
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UINT8 SGIR; ///< Offset 476 GPIO IRQ
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UINT8 RstPcieStorageInterfaceType[3]; ///< Offset 477 RST PCIe Storage Cycle Router#1 Interface Type
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///< Offset 478 RST PCIe Storage Cycle Router#2 Interface Type
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///< Offset 479 RST PCIe Storage Cycle Router#3 Interface Type
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UINT8 RstPcieStoragePmCapPtr[3]; ///< Offset 480 RST PCIe Storage Cycle Router#1 Power Management Capability Pointer
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///< Offset 481 RST PCIe Storage Cycle Router#2 Power Management Capability Pointer
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///< Offset 482 RST PCIe Storage Cycle Router#3 Power Management Capability Pointer
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UINT8 RstPcieStoragePcieCapPtr[3]; ///< Offset 483 RST PCIe Storage Cycle Router#1 PCIe Capabilities Pointer
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///< Offset 484 RST PCIe Storage Cycle Router#2 PCIe Capabilities Pointer
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///< Offset 485 RST PCIe Storage Cycle Router#3 PCIe Capabilities Pointer
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UINT16 RstPcieStorageL1ssCapPtr[3]; ///< Offset 486 RST PCIe Storage Cycle Router#1 L1SS Capability Pointer
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///< Offset 488 RST PCIe Storage Cycle Router#2 L1SS Capability Pointer
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///< Offset 490 RST PCIe Storage Cycle Router#3 L1SS Capability Pointer
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UINT8 RstPcieStorageEpL1ssControl2[3]; ///< Offset 492 RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2
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///< Offset 493 RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2
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///< Offset 494 RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2
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UINT32 RstPcieStorageEpL1ssControl1[3]; ///< Offset 495 RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1
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///< Offset 499 RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1
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///< Offset 503 RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1
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UINT16 RstPcieStorageLtrCapPtr[3]; ///< Offset 507 RST PCIe Storage Cycle Router#1 LTR Capability Pointer
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///< Offset 509 RST PCIe Storage Cycle Router#2 LTR Capability Pointer
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///< Offset 511 RST PCIe Storage Cycle Router#3 LTR Capability Pointer
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UINT32 RstPcieStorageEpLtrData[3]; ///< Offset 513 RST PCIe Storage Cycle Router#1 Endpoint LTR Data
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///< Offset 517 RST PCIe Storage Cycle Router#2 Endpoint LTR Data
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///< Offset 521 RST PCIe Storage Cycle Router#3 Endpoint LTR Data
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UINT16 RstPcieStorageEpLctlData16[3]; ///< Offset 525 RST PCIe Storage Cycle Router#1 Endpoint LCTL Data
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///< Offset 527 RST PCIe Storage Cycle Router#2 Endpoint LCTL Data
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///< Offset 529 RST PCIe Storage Cycle Router#3 Endpoint LCTL Data
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UINT16 RstPcieStorageEpDctlData16[3]; ///< Offset 531 RST PCIe Storage Cycle Router#1 Endpoint DCTL Data
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///< Offset 533 RST PCIe Storage Cycle Router#2 Endpoint DCTL Data
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///< Offset 535 RST PCIe Storage Cycle Router#3 Endpoint DCTL Data
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UINT16 RstPcieStorageEpDctl2Data16[3]; ///< Offset 537 RST PCIe Storage Cycle Router#1 Endpoint DCTL2 Data
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///< Offset 539 RST PCIe Storage Cycle Router#2 Endpoint DCTL2 Data
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///< Offset 541 RST PCIe Storage Cycle Router#3 Endpoint DCTL2 Data
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UINT16 RstPcieStorageRpDctl2Data16[3]; ///< Offset 543 RST PCIe Storage Cycle Router#1 RootPort DCTL2 Data
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///< Offset 545 RST PCIe Storage Cycle Router#2 RootPort DCTL2 Data
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///< Offset 547 RST PCIe Storage Cycle Router#3 RootPort DCTL2 Data
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UINT32 RstPcieStorageUniqueTableBar[3]; ///< Offset 549 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR
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///< Offset 553 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR
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///< Offset 557 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR
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UINT32 RstPcieStorageUniqueTableBarValue[3]; ///< Offset 561 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value
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///< Offset 565 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value
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///< Offset 569 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value
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UINT32 RstPcieStorageUniquePbaBar[3]; ///< Offset 573 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR
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///< Offset 577 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR
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///< Offset 581 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR
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UINT32 RstPcieStorageUniquePbaBarValue[3]; ///< Offset 585 RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value
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///< Offset 589 RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value
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///< Offset 593 RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value
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UINT32 RstPcieStorageRootPortNum[3]; ///< Offset 597 RST PCIe Storage Cycle Router#1 Root Port number
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///< Offset 601 RST PCIe Storage Cycle Router#2 Root Port number
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///< Offset 605 RST PCIe Storage Cycle Router#3 Root Port number
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UINT8 ExitBootServicesFlag; ///< Offset 609 Flag indicating Exit Boot Service, to inform SMM
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UINT32 SxMemBase; ///< Offset 610 Sx handler reserved MMIO base
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UINT32 SxMemSize; ///< Offset 614 Sx handler reserved MMIO size
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UINT8 Cio2EnabledAsAcpiDevice; ///< Offset 618 Cio2 Device Enabled as ACPI device
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UINT8 Cio2IrqNumber; ///< Offset 619 Cio2 Interrupt Number
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UINT8 ThermalDeviceAcpiEnabled; ///< Offset 620 Thermal Device Acpi mode enabled
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UINT8 ThermalDeviceInterruptLine; ///< Offset 621 Thermal Device IRQ number
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UINT32 XhciRsvdMemBase; ///< Offset 622 XHCI memory base address
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UINT8 EMH4; ///< Offset 626 eMMC HS400 mode enabled
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UINT8 EMDS; ///< Offset 627 eMMC Driver Strength
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UINT8 CpuSku; ///< Offset 628 CPU SKU
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UINT16 IoTrapAddress[4]; ///< Offset 629
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///< Offset 631
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///< Offset 633
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///< Offset 635
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UINT8 IoTrapStatus[4]; ///< Offset 637
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///< Offset 638
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///< Offset 639
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///< Offset 640
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UINT16 PMBS; ///< Offset 641 ACPI IO BASE address
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UINT32 PWRM; ///< Offset 643 PWRM MEM BASE address
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} PCH_NVS_AREA;
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#pragma pack(pop)
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#endif
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