/** @file
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The GUID definition for PchConfigHob
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Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _PCH_CONFIG_HOB_H_
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#define _PCH_CONFIG_HOB_H_
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#include <ConfigBlock.h>
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#include <PchAccess.h>
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#include <ConfigBlock/SmbusConfig.h>
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#include <ConfigBlock/InterruptConfig.h>
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#include <ConfigBlock/PcieRpConfig.h>
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#include <ConfigBlock/SataConfig.h>
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#include <ConfigBlock/FlashProtectionConfig.h>
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extern EFI_GUID gPchConfigHobGuid;
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#pragma pack (push,1)
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///
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/// This structure contains the HOB which are related to PCH general config.
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///
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typedef struct {
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/**
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This member describes whether or not the Compatibility Revision ID (CRID) feature
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of PCH should be enabled. <b>0: Disable</b>; 1: Enable
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**/
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UINT32 Crid : 1;
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} GENERAL_HOB;
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///
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/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
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///
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typedef struct {
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UINT8 RsvdBytes[3];
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UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
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/**
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Array of addresses reserved for non-ARP-capable SMBus devices.
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**/
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UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
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} SMBUS_HOB;
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///
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/// The INTERRUPT describes interrupt settings for PCH HOB.
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///
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typedef struct {
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UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
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UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
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UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4.
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PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
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} INTERRUPT_HOB;
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///
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/// The CIO2_HOB block describes SkyCam CIO2 device.
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///
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typedef struct {
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/**
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NOTE: For SKL PCH, while CIO2 is enabled,
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RC will configure CIO2 controller as ACPI mode when PCH stepping < C0, and configure to PCI mode for C0 onwards.
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**/
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UINT32 DeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled</b>
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UINT32 RsvdBits0 : 30;
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} CIO2_HOB;
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/**
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The SERIAL_IO block provides the configurations to set the Serial IO controllers
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to Acpi devices or Pci controllers, and also set the interrupt type to Acpi or Pci
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through Policy. It also provides to configure the I2c0 and I2c1 voltage
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to 1.8v or 3.3v by platform setting.
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Please refer to PeiDxeSmmPchSerialIoLib.h for definition of device numbers and enum values for the below fields
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**/
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typedef struct {
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/**
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0: Disabled; 1: ACPI Mode; <b>2: PCI Mode</b>; 3: Hidden mode, 4: Legacy UART mode, 5: Skip Init
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NOTE: Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNumber for all SerialIo UARTx,
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the PCD is more meaningful to represent the board design. It means, if PcdSerialIoUartDebugEnable is not 0,
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the board is designed to use the SerialIo UART for debug message and the PcdSerialIoUartNumber is dedicated
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to be Debug UART usage. Therefore, it should grayout the option from setup menu since no other options
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available for this UART controller on this board, and also override the policy default accordingly.
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While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure the UART controller by policy.
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NOTE: While DevMode is set to 5 (Skip Init), BIOS will not initialize this controller. Platform is resonsible for
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configuring this controller. If platform initializes the Serial IO controller in Hidden Mode, it MUST
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follow the predefined BAR address for the controller.
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**/
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UINT8 DevMode[PCH_SERIALIO_MAX_CONTROLLERS]; ///< serial io max controllers default is <b>11</b>.
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UINT8 Gpio; ///< 0: Disabled; <b>1: Enabled</b>.
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UINT32 DebugUartNumber : 2; ///< UART number for debug purpose. 0:UART0, 1: UART1, <b>2:UART2</b>
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UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug UART controller after post. 0: diabled, <b>1: enabled</b>
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UINT32 RsvdBits0 : 29;
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} SERIAL_IO_HOB;
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///
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/// The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
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///
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typedef struct {
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///
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/// These members describe the configuration of each PCH PCIe root port.
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///
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PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
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/**
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This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
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or leaving untouched.
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- <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b>
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- To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are
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presented for maximum power savings where possible.
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- To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device
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functionality.
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- 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability.
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**/
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UINT32 AllowNoLtrIccPllShutdown : 1;
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UINT32 RsvdBits0 : 31;
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} PCIERP_HOB;
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typedef struct {
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UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
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/**
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Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI table:
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**/
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UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; <b>2: 4ch array</b>; 3: 1ch array
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UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: <b>0: Disable</b>; 1: Enable
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UINT32 DspEndpointI2s : 1; ///< I2S enablement: <b>0: Disable</b>; 1: Enable
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UINT32 RsvdBits0 : 27; ///< Reserved bits
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/**
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Bitmask of supported DSP features:
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[BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
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[BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
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Default is <b>zero</b>.
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**/
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UINT32 DspFeatureMask;
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} HDAUDIO_HOB;
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typedef struct {
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///
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/// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
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///
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UINT32 Enable : 1;
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UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
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UINT32 RsvdBits0 : 30; ///< Reserved bits
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/**
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This member configures the features, property, and capability for each SATA port.
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**/
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PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
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/**
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This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
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**/
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PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
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} SATA_HOB;
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/**
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The THERMAL_HOB block describes the expected configuration of the PCH for Thermal.
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**/
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typedef struct {
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UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled in PCI mode</b>, 2: Enabled in ACPI mode
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UINT32 RsvdBits0 : 30; ///< Reserved bits
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} THERMAL_HOB;
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/**
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This structure is used for the emulation feature for Port61h read. The port is trapped
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and the SMI handler will toggle bit4 according to the handler's internal state.
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**/
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typedef struct {
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UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b> the emulation
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UINT32 RsvdBits0 : 31; ///< Reserved bits
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} PORT61H_SMM_HOB;
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///
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/// The SCS_HOB block describes Storage and Communication Subsystem (SCS) settings for PCH.
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///
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typedef struct {
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UINT32 ScsEmmcEnabled : 2; ///< Determine if eMMC is enabled - 0: Disabled, <b>1: Enabled</b>.
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UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC HS400 Mode if ScsEmmcEnabled - <b>0: Disabled</b>, 1: Enabled
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/**
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Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid. <b>0: Disabled</b>, 1: Enabled.
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First Boot or CMOS clear, system boot with Default settings, set tuning required.
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Subsequent Boots, Get Variable 'Hs400TuningData'
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- if failed to get variable, set tuning required
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- if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxDataDll from variable. Set tuning not required.
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**/
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UINT32 ScsEmmcHs400TuningRequired : 1;
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UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tuning Data Valid
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UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver strength: <b>0 - 33 Ohm</b>, 1 - 40 Ohm, 2 - 50 Ohm
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UINT32 RsvdBits : 24;
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} SCS_HOB;
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/**
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The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
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for security requirement.
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**/
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typedef struct {
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UINT32 GlobalSmi : 1;
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/**
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<b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
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Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>.
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**/
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UINT32 BiosInterface : 1;
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/**
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<b>(Test)</b> Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
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and lower 128-byte bank of RTC RAM. 0: Disable; <b>1: Enable</b>.
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**/
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UINT32 RtcLock : 1;
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/**
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Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
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for the BIOS region protection. When it is enabled, the BIOS Region can only be
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modified from SMM after EndOfDxe protocol is installed.
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Note: When BiosLock is enabled, platform code also needs to update to take care
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of BIOS modification (including SetVariable) in DXE or runtime phase after
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EndOfDxe protocol is installed. <b>0: Disable</b>; 1: Enable.
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**/
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UINT32 BiosLock : 1;
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UINT32 RsvdBits : 28;
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} LOCK_DOWN_HOB;
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/**
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The PM_HOB block describes expected miscellaneous power management settings.
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The PowerResetStatusClear field would clear the Power/Reset status bits, please
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set the bits if you want PCH Init driver to clear it, if you want to check the
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status later then clear the bits.
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**/
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typedef struct {
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/**
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<b>(Test)</b>
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When set to true, this bit disallows host reads to PMC XRAM.
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BIOS must set this bit (to disable and lock the feature) prior to passing control to OS
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0:Disable, <b>1:Enable</b>
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**/
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UINT32 PmcReadDisable : 1;
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UINT32 RsvdBits1 : 31;
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} PM_HOB;
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/**
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This structure contains the HOB which are related to P2SB device.
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**/
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typedef struct {
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/**
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<b>(Test)</b>
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This unlock the SBI lock bit to allow SBI after post time. <b>0: Disable</b>; 1: Enable.
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NOTE: Do not set this policy "SbiUnlock" unless necessary.
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**/
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UINT32 SbiUnlock : 1;
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/**
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<b>(Test)</b>
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The PSF registers will be locked before 3rd party code execution.
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This policy unlock the PSF space. <b>0: Disable</b>; 1: Enable.
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NOTE: Do not set this policy "SbAccessUnlock" unless necessary.
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**/
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UINT32 PsfUnlock : 1; //@deprecated
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UINT32 SbAccessUnlock : 1;
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UINT32 RsvdBits : 29;
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} P2SB_HOB;
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/**
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This structure holds information about disabled USB2 and USB3 ports through Port Disable Override functionality
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**/
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typedef struct {
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UINT32 DelayPdoProgramming : 1; ///< Flag informing about delaying PDO programming to DXE phase
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UINT32 Usb2DisabledPorts : 16; ///< USB2 Disabled ports
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UINT32 Usb3DisabledPorts : 10; ///< USB3 Disabled ports
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UINT32 RsvdBits : 5;
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} USB_HOB;
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///
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/// Pch Config Hob
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///
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typedef struct {
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EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for gPchConfigHobGuid
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GENERAL_HOB General; ///< Pch general HOB definition
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INTERRUPT_HOB Interrupt; ///< Interrupt HOB definition
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SERIAL_IO_HOB SerialIo; ///< Serial io HOB definition
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PCIERP_HOB PcieRp; ///< PCIE root port HOB definition
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THERMAL_HOB Thermal; ///< Thermal HOB definition
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SCS_HOB Scs; ///< Scs HOB definition
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CIO2_HOB Cio2; ///< CIO2 HOB definition
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LOCK_DOWN_HOB LockDown; ///< Lock down HOB definition
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PM_HOB Pm; ///< PM HOB definition
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P2SB_HOB P2sb; ///< P2sb HOB definition
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HDAUDIO_HOB HdAudio; ///< HD audio definition
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SATA_HOB Sata; ///< SATA definition
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PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];
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PORT61H_SMM_HOB Port61hSmm;
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SMBUS_HOB Smbus;
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USB_HOB Usb;
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} PCH_CONFIG_HOB;
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#pragma pack (pop)
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#endif
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